[llvm-commits] [llvm] r106805 - in /llvm/trunk: lib/CodeGen/MachineRegisterInfo.cpp test/CodeGen/ARM/long_shift.ll test/CodeGen/X86/sse3.ll
Dan Gohman
gohman at apple.com
Thu Jun 24 15:23:02 PDT 2010
Author: djg
Date: Thu Jun 24 17:23:02 2010
New Revision: 106805
URL: http://llvm.org/viewvc/llvm-project?rev=106805&view=rev
Log:
Teach EmitLiveInCopies to omit copies for unused virtual registers,
and to clean up unused incoming physregs from the live-in list.
Modified:
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
llvm/trunk/test/CodeGen/ARM/long_shift.ll
llvm/trunk/test/CodeGen/X86/sse3.ll
Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=106805&r1=106804&r2=106805&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Thu Jun 24 17:23:02 2010
@@ -182,21 +182,32 @@
const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII) {
// Emit the copies into the top of the block.
- for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
- E = livein_end(); LI != E; ++LI)
- if (LI->second) {
- const TargetRegisterClass *RC = getRegClass(LI->second);
- bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
- LI->second, LI->first, RC, RC,
- DebugLoc());
- assert(Emitted && "Unable to issue a live-in copy instruction!\n");
- (void) Emitted;
- }
+ for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
+ if (LiveIns[i].second) {
+ if (use_empty(LiveIns[i].second)) {
+ // The livein has no uses. Drop it.
+ //
+ // It would be preferable to have isel avoid creating live-in
+ // records for unused arguments in the first place, but it's
+ // complicated by the debug info code for arguments.
+ LiveIns.erase(LiveIns.begin() + i);
+ --i; --e;
+ } else {
+ // Emit a copy.
+ const TargetRegisterClass *RC = getRegClass(LiveIns[i].second);
+ bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
+ LiveIns[i].second, LiveIns[i].first,
+ RC, RC, DebugLoc());
+ assert(Emitted && "Unable to issue a live-in copy instruction!\n");
+ (void) Emitted;
- // Add function live-ins to entry block live-in set.
- for (MachineRegisterInfo::livein_iterator I = livein_begin(),
- E = livein_end(); I != E; ++I)
- EntryMBB->addLiveIn(I->first);
+ // Add the register to the entry block live-in set.
+ EntryMBB->addLiveIn(LiveIns[i].first);
+ }
+ } else {
+ // Add the register to the entry block live-in set.
+ EntryMBB->addLiveIn(LiveIns[i].first);
+ }
}
void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
Modified: llvm/trunk/test/CodeGen/ARM/long_shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long_shift.ll?rev=106805&r1=106804&r2=106805&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/long_shift.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/long_shift.ll Thu Jun 24 17:23:02 2010
@@ -23,10 +23,10 @@
define i32 @f2(i64 %x, i64 %y) {
; CHECK: f2
; CHECK: mov r0, r0, lsr r2
-; CHECK-NEXT: rsb r12, r2, #32
+; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: sub r2, r2, #32
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: orr r0, r0, r1, lsl r12
+; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: movge r0, r1, asr r2
%a = ashr i64 %x, %y
%b = trunc i64 %a to i32
@@ -36,10 +36,10 @@
define i32 @f3(i64 %x, i64 %y) {
; CHECK: f3
; CHECK: mov r0, r0, lsr r2
-; CHECK-NEXT: rsb r12, r2, #32
+; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: sub r2, r2, #32
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: orr r0, r0, r1, lsl r12
+; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: movge r0, r1, lsr r2
%a = lshr i64 %x, %y
%b = trunc i64 %a to i32
Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=106805&r1=106804&r2=106805&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Thu Jun 24 17:23:02 2010
@@ -63,10 +63,10 @@
ret <8 x i16> %tmp
; X64: t4:
; X64: pextrw $7, %xmm0, %eax
-; X64: pshufhw $100, %xmm0, %xmm2
-; X64: pinsrw $1, %eax, %xmm2
+; X64: pshufhw $100, %xmm0, %xmm1
+; X64: pinsrw $1, %eax, %xmm1
; X64: pextrw $1, %xmm0, %eax
-; X64: movdqa %xmm2, %xmm0
+; X64: movdqa %xmm1, %xmm0
; X64: pinsrw $4, %eax, %xmm0
; X64: ret
}
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