[llvm-commits] [llvm] r106693 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h test/CodeGen/ARM/lsr-on-unrolled-loops.ll

[Jakob Stoklund Olesen]

On Jun 23, 2010, at 4:46 PM, Dale Johannesen wrote:

> 
> On Jun 23, 2010, at 4:00 PMPDT, Bill Wendling wrote:
> 
>> Author: void
>> Date: Wed Jun 23 18:00:16 2010
>> New Revision: 106693
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=106693&view=rev
>> Log:
>> We are missing opportunites to use ldm. Take code like this:
>> 
>> void t(int *cp0, int *cp1, int *dp, int fmd) {
>> int c0, c1, d0, d1, d2, d3;
>> c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
>> c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
>> /* ... */
>> }
> 
> You can't combine volatile loads, is there a check for this?

Yes, the ARMLoadStoreOptimizer checks for that.

Unaligned LDM/STM is also not allowed.

> I'm also wondering if interference could be a problem, where one  
> pointer points to the other one.  I think it's OK as long as there are  
> no stores, as in the example. 

Only loads off the same DAG chain are scheduled together. So if the DAG chains are correct we should be fine.