[llvm-commits] [llvm] r106762 - in /llvm/trunk: lib/Target/ARM/Thumb2SizeReduction.cpp test/CodeGen/Thumb2/thumb2-eor.ll test/CodeGen/Thumb2/thumb2-uxtb.ll

[Bob Wilson]

Author: bwilson
Date: Thu Jun 24 11:50:20 2010
New Revision: 106762

URL: http://llvm.org/viewvc/llvm-project?rev=106762&view=rev
Log:
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
form so they can be narrowed to 16-bit instructions.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
    llvm/trunk/test/CodeGen/Thumb2/thumb2-eor.ll
    llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=106762&r1=106761&r2=106762&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Jun 24 11:50:20 2010
@@ -451,11 +451,18 @@
   if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
     return false;
 
-  const TargetInstrDesc &TID = MI->getDesc();
   unsigned Reg0 = MI->getOperand(0).getReg();
   unsigned Reg1 = MI->getOperand(1).getReg();
-  if (Reg0 != Reg1)
-    return false;
+  if (Reg0 != Reg1) {
+    // Try to commute the operands to make it a 2-address instruction.
+    unsigned CommOpIdx1, CommOpIdx2;
+    if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
+        CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
+      return false;
+    MachineInstr *CommutedMI = TII->commuteInstruction(MI);
+    if (!CommutedMI)
+      return false;
+  }
   if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
     return false;
   if (Entry.Imm2Limit) {
@@ -484,6 +491,7 @@
 
   bool HasCC = false;
   bool CCDead = false;
+  const TargetInstrDesc &TID = MI->getDesc();
   if (TID.hasOptionalDef()) {
     unsigned NumOps = TID.getNumOperands();
     HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-eor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-eor.ll?rev=106762&r1=106761&r2=106762&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-eor.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-eor.ll Thu Jun 24 11:50:20 2010
@@ -9,11 +9,18 @@
 
 define i32 @f2(i32 %a, i32 %b) {
 ; CHECK: f2:
-; CHECK: eor.w r0, r1, r0
+; CHECK: eors r0, r1
     %tmp = xor i32 %b, %a
     ret i32 %tmp
 }
 
+define i32 @f2b(i32 %a, i32 %b, i32 %c) {
+; CHECK: f2b:
+; CHECK: eor.w r0, r1, r2
+    %tmp = xor i32 %b, %c
+    ret i32 %tmp
+}
+
 define i32 @f3(i32 %a, i32 %b) {
 ; CHECK: f3:
 ; CHECK: eor.w r0, r0, r1, lsl #5

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll?rev=106762&r1=106761&r2=106762&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll Thu Jun 24 11:50:20 2010
@@ -87,7 +87,7 @@
 ; CHECK: and.w r0, r1, r0, lsr #7
 ; CHECK: lsrs  r1, r0, #5
 ; CHECK: uxtb16  r1, r1
-; CHECK: orr.w r0, r1, r0
+; CHECK: orrs r0, r1
 
 	%tmp1 = lshr i32 %p0, 7		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 16253176		; <i32> [#uses=2]