[llvm-commits] [llvm] r106753 - in /llvm/trunk: include/llvm/CodeGen/RegisterCoalescer.h lib/CodeGen/RegisterCoalescer.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Thu Jun 24 09:19:28 PDT 2010
Author: stoklund
Date: Thu Jun 24 11:19:28 2010
New Revision: 106753
URL: http://llvm.org/viewvc/llvm-project?rev=106753&view=rev
Log:
Be more strict about subreg-to-subreg copies in CoalescerPair.
Also keep track of the original DstREg before subregister adjustments.
Modified:
llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Modified: llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h?rev=106753&r1=106752&r2=106753&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h Thu Jun 24 11:19:28 2010
@@ -165,9 +165,15 @@
/// virtual register.
unsigned subIdx_;
+ /// origDstReg_ - dstReg_ without subreg adjustments.
+ unsigned origDstReg_;
+
/// partial_ - True when the original copy was a partial subregister copy.
bool partial_;
+ /// crossClass_ - True when both regs are virtual, and newRC is constrained.
+ bool crossClass_;
+
/// flipped_ - True when DstReg and SrcReg are reversed from the oriignal copy
/// instruction.
bool flipped_;
@@ -186,7 +192,8 @@
public:
CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri)
: tii_(tii), tri_(tri), dstReg_(0), srcReg_(0), subIdx_(0),
- partial_(false), flipped_(false), newRC_(0) {}
+ origDstReg_(0), partial_(false), crossClass_(false), flipped_(false),
+ newRC_(0) {}
/// setRegisters - set registers to match the copy instruction MI. Return
/// false if MI is not a coalescable copy instruction.
@@ -207,6 +214,9 @@
/// full register, but was a subreg operation.
bool isPartial() const { return partial_; }
+ /// isCrossClass - Return true if DstReg is virtual and NewRC is a smaller register class than DstReg's.
+ bool isCrossClass() const { return crossClass_; }
+
/// isFlipped - Return true when getSrcReg is the register being defined by
/// the original copy instruction.
bool isFlipped() const { return flipped_; }
@@ -222,6 +232,10 @@
/// coalesced into, or 0.
unsigned getSubIdx() const { return subIdx_; }
+ /// getOrigDstReg - Return DstReg as it appeared in the original copy
+ /// instruction before any subreg adjustments.
+ unsigned getOrigDstReg() const { return isPhys() ? origDstReg_ : dstReg_; }
+
/// getNewRC - Return the register class of the coalesced register.
const TargetRegisterClass *getNewRC() const { return newRC_; }
};
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=106753&r1=106752&r2=106753&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jun 24 11:19:28 2010
@@ -63,7 +63,7 @@
bool CoalescerPair::setRegisters(const MachineInstr *MI) {
srcReg_ = dstReg_ = subIdx_ = 0;
newRC_ = 0;
- flipped_ = false;
+ flipped_ = crossClass_ = false;
unsigned Src, Dst, SrcSub, DstSub;
if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub))
@@ -78,6 +78,7 @@
std::swap(SrcSub, DstSub);
flipped_ = true;
}
+ origDstReg_ = Dst;
const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
@@ -100,11 +101,19 @@
} else {
// Both registers are virtual.
- // Identical sub to sub.
- if (SrcSub == DstSub)
+ // Both registers have subreg indices.
+ if (SrcSub && DstSub) {
+ // For now we only handle the case of identical indices in commensurate
+ // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
+ // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
+ if (SrcSub != DstSub)
+ return false;
+ const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
+ const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
+ if (!getCommonSubClass(DstRC, SrcRC))
+ return false;
SrcSub = DstSub = 0;
- else if (SrcSub && DstSub)
- return false; // FIXME: Qreg:ssub_3 + Dreg:ssub_1 => QReg:dsub_1 + Dreg.
+ }
// There can be no SrcSub.
if (SrcSub) {
@@ -124,6 +133,7 @@
newRC_ = getCommonSubClass(DstRC, SrcRC);
if (!newRC_)
return false;
+ crossClass_ = newRC_ != DstRC || newRC_ != SrcRC;
}
// Check our invariants
assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
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