[llvm-commits] [llvm] r106643 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll

[Bill Wendling]

Author: void
Date: Wed Jun 23 13:16:24 2010
New Revision: 106643

URL: http://llvm.org/viewvc/llvm-project?rev=106643&view=rev
Log:
MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node
into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=106643&r1=106642&r2=106643&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Jun 23 13:16:24 2010
@@ -110,17 +110,35 @@
 static void AddFlags(SDNode *N, SDValue Flag, bool AddFlag,
                      SelectionDAG *DAG) {
   SmallVector<EVT, 4> VTs;
+
   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
     VTs.push_back(N->getValueType(i));
+
   if (AddFlag)
     VTs.push_back(MVT::Flag);
+
   SmallVector<SDValue, 4> Ops;
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
     Ops.push_back(N->getOperand(i));
+
   if (Flag.getNode())
     Ops.push_back(Flag);
+
   SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size());
+  MachineSDNode::mmo_iterator Begin = 0, End = 0;
+  MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
+
+  // Store memory references.
+  if (MN) {
+    Begin = MN->memoperands_begin();
+    End = MN->memoperands_end();
+  }
+
   DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size());
+
+  // Reset the memory references
+  if (MN)
+    MN->setMemRefs(Begin, End);
 }
 
 /// ClusterNeighboringLoads - Force nearby loads together by "flagging" them.
@@ -196,13 +214,16 @@
   // ensure they are scheduled in order of increasing addresses.
   SDNode *Lead = Loads[0];
   AddFlags(Lead, SDValue(0,0), true, DAG);
+
   SDValue InFlag = SDValue(Lead, Lead->getNumValues()-1);
   for (unsigned i = 1, e = Loads.size(); i != e; ++i) {
     bool OutFlag = i < e-1;
     SDNode *Load = Loads[i];
     AddFlags(Load, InFlag, OutFlag, DAG);
+
     if (OutFlag)
       InFlag = SDValue(Load, Load->getNumValues()-1);
+
     ++LoadsClustered;
   }
 }

Modified: llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll?rev=106643&r1=106642&r2=106643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll Wed Jun 23 13:16:24 2010
@@ -9,11 +9,11 @@
 ; lowering of arguments potentially overwrites the value.
 ;
 ; Move return address (76(%esp)) to a temporary register (%ebp)
-; CHECK: movl 76(%esp), %ebp
+; CHECK: movl 76(%esp), [[REGISTER:%[a-z]+]]
 ; Overwrite return addresss
-; CHECK: movl %ecx, 76(%esp)
+; CHECK: movl %ebx, 76(%esp)
 ; Move return address from temporary register (%ebp) to new stack location (60(%esp))
-; CHECK: movl %ebp, 60(%esp)
+; CHECK: movl [[REGISTER]], 60(%esp)
 
 %tupl_p = type [9 x i32]*