[llvm-commits] [llvm] r106413 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Rafael Espindola
rafael.espindola at gmail.com
Mon Jun 21 06:31:32 PDT 2010
Author: rafael
Date: Mon Jun 21 08:31:32 2010
New Revision: 106413
URL: http://llvm.org/viewvc/llvm-project?rev=106413&view=rev
Log:
Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=106413&r1=106412&r2=106413&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jun 21 08:31:32 2010
@@ -1890,26 +1890,6 @@
return X86::GR8_ABCD_HRegClass.contains(Reg);
}
-
-static const TargetRegisterClass *findCommonRC(const TargetRegisterClass *a,
- const TargetRegisterClass *b) {
- if (a == b)
- return a;
- if (a->hasSuperClass(b))
- return b;
- if (b->hasSuperClass(a))
- return a;
- for (TargetRegisterClass::sc_iterator i = a->superclasses_begin(),
- e = a->superclasses_end();
- i != e;
- ++i) {
- const TargetRegisterClass *s = *i;
- if (b->hasSuperClass(s))
- return s;
- }
- return NULL;
-}
-
bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
@@ -1918,7 +1898,24 @@
DebugLoc DL) const {
// Determine if DstRC and SrcRC have a common superclass in common.
- const TargetRegisterClass *CommonRC = findCommonRC(SrcRC, DestRC);
+ const TargetRegisterClass *CommonRC = DestRC;
+ if (DestRC == SrcRC)
+ /* Source and destination have the same register class. */;
+ else if (CommonRC->hasSuperClass(SrcRC))
+ CommonRC = SrcRC;
+ else if (!DestRC->hasSubClass(SrcRC)) {
+ // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
+ // but we want to copy them as GR64. Similarly, for GR32_NOREX and
+ // GR32_NOSP, copy as GR32.
+ if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
+ DestRC->hasSuperClass(&X86::GR64RegClass))
+ CommonRC = &X86::GR64RegClass;
+ else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
+ DestRC->hasSuperClass(&X86::GR32RegClass))
+ CommonRC = &X86::GR32RegClass;
+ else
+ CommonRC = 0;
+ }
if (CommonRC) {
unsigned Opc;
@@ -1984,41 +1981,29 @@
return true;
}
- if (X86::RSTRegClass.contains(SrcReg))
- CommonRC = DestRC;
- else if (X86::RSTRegClass.contains(DestReg))
- CommonRC = SrcRC;
- else if (X86::CCRRegClass.contains(SrcReg))
- CommonRC = DestRC;
- else if (X86::CCRRegClass.contains(DestReg))
- CommonRC = SrcRC;
-
- if (!CommonRC)
- return false;
-
// Moving EFLAGS to / from another register requires a push and a pop.
- if (X86::CCRRegClass.contains(SrcReg)) {
+ if (SrcRC == &X86::CCRRegClass) {
if (SrcReg != X86::EFLAGS)
return false;
- if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
+ if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
BuildMI(MBB, MI, DL, get(X86::PUSHF64));
BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
return true;
- } else if (CommonRC == &X86::GR32RegClass ||
- CommonRC == &X86::GR32_NOSPRegClass) {
+ } else if (DestRC == &X86::GR32RegClass ||
+ DestRC == &X86::GR32_NOSPRegClass) {
BuildMI(MBB, MI, DL, get(X86::PUSHF32));
BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
return true;
}
- } else if (X86::CCRRegClass.contains(DestReg)) {
+ } else if (DestRC == &X86::CCRRegClass) {
if (DestReg != X86::EFLAGS)
return false;
- if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
+ if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, DL, get(X86::POPF64));
return true;
- } else if (CommonRC == &X86::GR32RegClass ||
- CommonRC == &X86::GR32_NOSPRegClass) {
+ } else if (SrcRC == &X86::GR32RegClass ||
+ DestRC == &X86::GR32_NOSPRegClass) {
BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, DL, get(X86::POPF32));
return true;
@@ -2026,19 +2011,19 @@
}
// Moving from ST(0) turns into FpGET_ST0_32 etc.
- if (X86::RSTRegClass.contains(SrcReg)) {
+ if (SrcRC == &X86::RSTRegClass) {
// Copying from ST(0)/ST(1).
if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
// Can only copy from ST(0)/ST(1) right now
return false;
bool isST0 = SrcReg == X86::ST0;
unsigned Opc;
- if (CommonRC == &X86::RFP32RegClass)
+ if (DestRC == &X86::RFP32RegClass)
Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
- else if (CommonRC == &X86::RFP64RegClass)
+ else if (DestRC == &X86::RFP64RegClass)
Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
else {
- if (CommonRC != &X86::RFP80RegClass)
+ if (DestRC != &X86::RFP80RegClass)
return false;
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
}
@@ -2047,19 +2032,19 @@
}
// Moving to ST(0) turns into FpSET_ST0_32 etc.
- if (X86::RSTRegClass.contains(DestReg)) {
+ if (DestRC == &X86::RSTRegClass) {
// Copying to ST(0) / ST(1).
if (DestReg != X86::ST0 && DestReg != X86::ST1)
// Can only copy to TOS right now
return false;
bool isST0 = DestReg == X86::ST0;
unsigned Opc;
- if (CommonRC == &X86::RFP32RegClass)
+ if (SrcRC == &X86::RFP32RegClass)
Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
- else if (CommonRC == &X86::RFP64RegClass)
+ else if (SrcRC == &X86::RFP64RegClass)
Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
else {
- if (CommonRC != &X86::RFP80RegClass)
+ if (SrcRC != &X86::RFP80RegClass)
return false;
Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
}
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