[llvm-commits] [llvm] r106360 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
Dan Gohman
gohman at apple.com
Fri Jun 18 17:02:06 PDT 2010
Author: djg
Date: Fri Jun 18 19:02:06 2010
New Revision: 106360
URL: http://llvm.org/viewvc/llvm-project?rev=106360&view=rev
Log:
Silence compiler warnings.
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=106360&r1=106359&r2=106360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Jun 18 19:02:06 2010
@@ -2290,7 +2290,7 @@
"Reg operand expected");
RegClass = OpInfo[OpIdx].RegClass;
- while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
+ while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
MI.addOperand(MCOperand::CreateReg(
getRegisterEnum(B, RegClass, Rd,
UseDRegPair(Opcode))));
@@ -2310,7 +2310,7 @@
// possible TIED_TO DPR/QPR's (ignored), then possible lane index.
RegClass = OpInfo[0].RegClass;
- while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
+ while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
MI.addOperand(MCOperand::CreateReg(
getRegisterEnum(B, RegClass, Rd,
UseDRegPair(Opcode))));
@@ -2336,7 +2336,7 @@
++OpIdx;
}
- while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
+ while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
"Tied to operand expected");
MI.addOperand(MCOperand::CreateReg(0));
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