[llvm-commits] [llvm] r106349 - in /llvm/trunk/lib/Target/X86: X86InstrFormats.td X86InstrSSE.td
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Fri Jun 18 16:13:35 PDT 2010
Author: bruno
Date: Fri Jun 18 18:13:35 2010
New Revision: 106349
URL: http://llvm.org/viewvc/llvm-project?rev=106349&view=rev
Log:
Apply some refactor to packed instructions
Modified:
llvm/trunk/lib/Target/X86/X86InstrFormats.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=106349&r1=106348&r2=106349&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Fri Jun 18 18:13:35 2010
@@ -225,6 +225,18 @@
let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
}
+// PI - SSE 1 & 2 packed instructions
+class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
+ Domain d>
+ : I<o, F, outs, ins, asm, pattern, d> {
+ let Predicates = !if(hasVEX_4VPrefix /* VEX_4V */,
+ !if(hasOpSizePrefix /* OpSize */, [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
+ !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
+
+ // AVX instructions have a 'v' prefix in the mnemonic
+ let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
+}
+
// SSE1 Instruction Templates:
//
// SSI - SSE1 instructions with XS prefix.
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=106349&r1=106348&r2=106349&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jun 18 18:13:35 2010
@@ -657,6 +657,19 @@
OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
}
+/// sse12_fp_packed - SSE 1 & 2 packed instructions class
+multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ RegisterClass RC, ValueType vt,
+ X86MemOperand x86memop, PatFrag mem_frag,
+ Domain d> {
+ let isCommutable = 1 in
+ def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
+ OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
+ def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
+ OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
+ (mem_frag addr:$src2)))],d>;
+}
+
/// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
/// vector forms.
///
@@ -673,7 +686,6 @@
SDNode OpNode, bit Commutable = 0> {
let Constraints = "", isAsmParserOnly = 1 in {
- // Scalar operation, reg+reg.
defm V#NAME#SS : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
OpNode, FR32, f32mem>, XS, VEX_4V;
@@ -681,78 +693,34 @@
defm V#NAME#SD : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
OpNode, FR64, f64mem>, XD, VEX_4V;
+
+ defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+ "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
+ VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
+ VEX_4V;
+
+ defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+ "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
+ VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
+ OpSize, VEX_4V;
}
let Constraints = "$src1 = $dst" in {
- // Scalar operation, reg+reg.
defm SS : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
OpNode, FR32, f32mem>, XS;
+
defm SD : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
OpNode, FR64, f64mem>, XD;
- }
-
- // Vector operation, reg+reg.
- def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
- let isCommutable = Commutable;
- }
-
- def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
- let isCommutable = Commutable;
- }
- def V#NAME#PSrr : VPSI<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr,
- "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []> {
- let isCommutable = Commutable;
- let Constraints = "";
- let isAsmParserOnly = 1;
- }
-
- def V#NAME#PDrr : VPDI<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr,
- "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []> {
- let isCommutable = Commutable;
- let Constraints = "";
- let isAsmParserOnly = 1;
- }
-
- // Vector operation, reg+mem.
- def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, f128mem:$src2),
- !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
-
- def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, f128mem:$src2),
- !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
-
- def V#NAME#PSrm : VPSI<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, f128mem:$src2),
- !strconcat(OpcodeStr,
- "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []> {
- let Constraints = "";
- let isAsmParserOnly = 1;
- }
-
- def V#NAME#PDrm : VPDI<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, f128mem:$src2),
- !strconcat(OpcodeStr,
- "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []> {
- let Constraints = "";
- let isAsmParserOnly = 1;
+ defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+ "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
+ f128mem, memopv4f32, SSEPackedSingle>, TB;
+
+ defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
+ "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
+ f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
}
// Intrinsic operation, reg+reg.
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