[llvm-commits] [llvm] r106296 - in /llvm/trunk: include/llvm/CodeGen/MachineRegisterInfo.h include/llvm/Target/TargetInstrDesc.h include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/MachineRegisterInfo.cpp lib/Target/ARM/Disassembler/ARMDisassemb
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Fri Jun 18 14:14:10 PDT 2010
Hi Dan,
This is generating the following warnings:
/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp: In function
‘bool DisassembleNLdSt0(llvm::MCInst&, unsigned int, uint32_t, short
unsigned int, unsigned int&, bool, bool, llvm::ARMBasicMCBuilder*)’:
llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp:2293:
warning: comparison between signed and unsigned integer expressions
/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp:2313:
warning: comparison between signed and unsigned integer expressions
/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp:2339:
warning: comparison between signed and unsigned integer expressions
On Fri, Jun 18, 2010 at 11:13 AM, Dan Gohman <gohman at apple.com> wrote:
> Author: djg
> Date: Fri Jun 18 13:13:55 2010
> New Revision: 106296
>
> URL: http://llvm.org/viewvc/llvm-project?rev=106296&view=rev
> Log:
> Start TargetRegisterClass indices at 0 instead of 1, so that
> MachineRegisterInfo doesn't have to confusingly allocate an extra
> entry.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
> llvm/trunk/include/llvm/Target/TargetInstrDesc.h
> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
> llvm/trunk/lib/Target/TargetInstrInfo.cpp
> llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
> llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Fri Jun 18 13:13:55 2010
> @@ -35,7 +35,7 @@
> /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
> /// virtual registers. For each target register class, it keeps a list of
> /// virtual registers belonging to the class.
> - std::vector<std::vector<unsigned> > RegClass2VRegMap;
> + std::vector<unsigned> *RegClass2VRegMap;
>
> /// RegAllocHints - This vector records register allocation hints for virtual
> /// registers. For each virtual register, it keeps a register and hint type
>
> Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Fri Jun 18 13:13:55 2010
> @@ -55,7 +55,7 @@
> ///
> /// NOTE: This member should be considered to be private, all access should go
> /// through "getRegClass(TRI)" below.
> - unsigned short RegClass;
> + short RegClass;
>
> /// Flags - These are flags from the TOI::OperandFlags enum.
> unsigned short Flags;
>
> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Jun 18 13:13:55 2010
> @@ -523,8 +523,8 @@
> /// getRegClass - Returns the register class associated with the enumeration
> /// value. See class TargetOperandInfo.
> const TargetRegisterClass *getRegClass(unsigned i) const {
> - assert(i <= getNumRegClasses() && "Register Class ID out of range");
> - return i ? RegClassBegin[i - 1] : NULL;
> + assert(i < getNumRegClasses() && "Register Class ID out of range");
> + return RegClassBegin[i];
> }
>
> /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
>
> Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Fri Jun 18 13:13:55 2010
> @@ -20,7 +20,7 @@
> MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
> VRegInfo.reserve(256);
> RegAllocHints.reserve(256);
> - RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
> + RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()];
> UsedPhysRegs.resize(TRI.getNumRegs());
>
> // Create the physreg use/def lists.
> @@ -52,7 +52,7 @@
> // Remove from old register class's vregs list. This may be slow but
> // fortunately this operation is rarely needed.
> std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
> - std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
> + std::vector<unsigned>::iterator I = std::find(VRegs.begin(), VRegs.end(), VR);
> VRegs.erase(I);
>
> // Add to new register class's vregs list.
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Jun 18 13:13:55 2010
> @@ -765,7 +765,7 @@
> || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
> "Unexpected Opcode");
>
> - assert(NumOps >= 1 && OpInfo[0].RegClass == 0 && "Reg operand expected");
> + assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Reg operand expected");
>
> int Imm32 = 0;
> if (Opcode == ARM::SMC) {
> @@ -1106,7 +1106,7 @@
>
> assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
> (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
> - (OpInfo[OpIdx+2].RegClass == 0) &&
> + (OpInfo[OpIdx+2].RegClass < 0) &&
> "Expect 3 reg operands");
>
> // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
> @@ -1201,7 +1201,7 @@
> return false;
>
> assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
> - (OpInfo[OpIdx+1].RegClass == 0) &&
> + (OpInfo[OpIdx+1].RegClass < 0) &&
> "Expect 1 reg operand followed by 1 imm operand");
>
> ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
> @@ -1323,7 +1323,7 @@
> return false;
>
> assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
> - (OpInfo[OpIdx+1].RegClass == 0) &&
> + (OpInfo[OpIdx+1].RegClass < 0) &&
> "Expect 1 reg operand followed by 1 imm operand");
>
> ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
> @@ -1494,7 +1494,7 @@
>
> // If there is still an operand info left which is an immediate operand, add
> // an additional imm5 LSL/ASR operand.
> - if (ThreeReg && OpInfo[OpIdx].RegClass == 0
> + if (ThreeReg && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> // Extract the 5-bit immediate field Inst{11-7}.
> unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
> @@ -1540,7 +1540,7 @@
>
> // If there is still an operand info left which is an immediate operand, add
> // an additional rotate immediate operand.
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> // Extract the 2-bit rotate field Inst{11-10}.
> unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
> @@ -1725,7 +1725,7 @@
> "Tied to operand expected");
> MI.addOperand(MI.getOperand(0));
>
> - assert(OpInfo[2].RegClass == 0 && !OpInfo[2].isPredicate() &&
> + assert(OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() &&
> !OpInfo[2].isOptionalDef() && "Imm operand expected");
> MI.addOperand(MCOperand::CreateImm(fbits));
>
> @@ -1984,7 +1984,7 @@
> ++OpIdx;
>
> // Extract/decode the f64/f32 immediate.
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> // The asm syntax specifies the before-expanded <imm>.
> // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
> @@ -2273,7 +2273,7 @@
> }
>
> assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
> - OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected");
> + OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
> MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
> Rn)));
> MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
> @@ -2299,7 +2299,7 @@
> }
>
> // Handle possible lane index.
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
> ++OpIdx;
> @@ -2325,7 +2325,7 @@
> }
>
> assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
> - OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected");
> + OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
> MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
> Rn)));
> MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
> @@ -2344,7 +2344,7 @@
> }
>
> // Handle possible lane index.
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
> ++OpIdx;
> @@ -2408,7 +2408,7 @@
> assert(NumOps >= 2 &&
> (OpInfo[0].RegClass == ARM::DPRRegClassID ||
> OpInfo[0].RegClass == ARM::QPRRegClassID) &&
> - (OpInfo[1].RegClass == 0) &&
> + (OpInfo[1].RegClass < 0) &&
> "Expect 1 reg operand followed by 1 imm operand");
>
> // Qd/Dd = Inst{22:15-12} => NEON Rd
> @@ -2522,7 +2522,7 @@
> }
>
> // Add the imm operand, if required.
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
>
> unsigned imm = 0xFFFFFFFF;
> @@ -2602,7 +2602,7 @@
> decodeNEONRm(insn))));
> ++OpIdx;
>
> - assert(OpInfo[OpIdx].RegClass == 0 && "Imm operand expected");
> + assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected");
>
> // Add the imm operand.
>
> @@ -2732,7 +2732,7 @@
> getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
> ++OpIdx;
>
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> // Add the imm operand.
> unsigned Imm = 0;
> @@ -2857,7 +2857,7 @@
> assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
> OpInfo[0].RegClass == ARM::GPRRegClassID &&
> OpInfo[1].RegClass == ARM::DPRRegClassID &&
> - OpInfo[2].RegClass == 0 &&
> + OpInfo[2].RegClass < 0 &&
> "Expect >= 3 operands with one dst operand");
>
> ElemSize esize =
> @@ -2893,7 +2893,7 @@
> OpInfo[1].RegClass == ARM::DPRRegClassID &&
> TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
> OpInfo[2].RegClass == ARM::GPRRegClassID &&
> - OpInfo[3].RegClass == 0 &&
> + OpInfo[3].RegClass < 0 &&
> "Expect >= 3 operands with one dst operand");
>
> ElemSize esize =
> @@ -3203,7 +3203,8 @@
> // a pair of TargetOperandInfos with isPredicate() property.
> if (NumOpsRemaining >= 2 &&
> OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
> - OpInfo[Idx].RegClass == 0 && OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
> + OpInfo[Idx].RegClass < 0 &&
> + OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
> {
> // If we are inside an IT block, get the IT condition bits maintained via
> // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
> @@ -3235,7 +3236,8 @@
> // a pair of TargetOperandInfos with isPredicate() property.
> if (NumOpsRemaining >= 2 &&
> OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
> - OpInfo[Idx].RegClass == 0 && OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
> + OpInfo[Idx].RegClass < 0 &&
> + OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
> {
> // If we are inside an IT block, get the IT condition bits maintained via
> // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Fri Jun 18 13:13:55 2010
> @@ -395,7 +395,7 @@
> MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
> getT1tRm(insn))));
> } else {
> - assert(OpInfo[OpIdx].RegClass == 0 &&
> + assert(OpInfo[OpIdx].RegClass < 0 &&
> !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
> && "Pure imm operand expected");
> MI.addOperand(MCOperand::CreateImm(UseRt ? getT1Imm8(insn)
> @@ -531,7 +531,7 @@
> if (!OpInfo) return false;
>
> assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
> - (OpInfo[1].RegClass == 0 &&
> + (OpInfo[1].RegClass < 0 &&
> !OpInfo[1].isPredicate() &&
> !OpInfo[1].isOptionalDef())
> && "Invalid arguments");
> @@ -598,7 +598,7 @@
>
> assert(OpIdx < NumOps && "More operands expected");
>
> - if (OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate() &&
> + if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
> !OpInfo[OpIdx].isOptionalDef()) {
>
> MI.addOperand(MCOperand::CreateImm(Imm5 ? getT1Imm5(insn) : 0));
> @@ -632,7 +632,7 @@
> assert(NumOps >= 3 &&
> OpInfo[0].RegClass == ARM::tGPRRegClassID &&
> OpInfo[1].RegClass == ARM::GPRRegClassID &&
> - (OpInfo[2].RegClass == 0 &&
> + (OpInfo[2].RegClass < 0 &&
> !OpInfo[2].isPredicate() &&
> !OpInfo[2].isOptionalDef())
> && "Invalid arguments");
> @@ -658,7 +658,7 @@
> if (!OpInfo) return false;
>
> assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
> - (OpInfo[1].RegClass == 0 &&
> + (OpInfo[1].RegClass < 0 &&
> !OpInfo[1].isPredicate() &&
> !OpInfo[1].isOptionalDef())
> && "Invalid arguments");
> @@ -685,7 +685,7 @@
> assert(NumOps >= 3 &&
> OpInfo[0].RegClass == ARM::tGPRRegClassID &&
> OpInfo[1].RegClass == ARM::GPRRegClassID &&
> - (OpInfo[2].RegClass == 0 &&
> + (OpInfo[2].RegClass < 0 &&
> !OpInfo[2].isPredicate() &&
> !OpInfo[2].isOptionalDef())
> && "Invalid arguments");
> @@ -761,7 +761,7 @@
> // Predicate operands are handled elsewhere.
> if (NumOps == 2 &&
> OpInfo[0].isPredicate() && OpInfo[1].isPredicate() &&
> - OpInfo[0].RegClass == 0 && OpInfo[1].RegClass == ARM::CCRRegClassID) {
> + OpInfo[0].RegClass < 0 && OpInfo[1].RegClass == ARM::CCRRegClassID) {
> return true;
> }
>
> @@ -808,7 +808,7 @@
> }
>
> assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
> - (OpInfo[1].RegClass==0 || OpInfo[1].RegClass==ARM::tGPRRegClassID)
> + (OpInfo[1].RegClass < 0 || OpInfo[1].RegClass==ARM::tGPRRegClassID)
> && "Expect >=2 operands");
>
> // Add the destination operand.
> @@ -913,7 +913,7 @@
> const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
> if (!OpInfo) return false;
>
> - assert(NumOps == 3 && OpInfo[0].RegClass == 0 &&
> + assert(NumOps == 3 && OpInfo[0].RegClass < 0 &&
> OpInfo[1].isPredicate() && OpInfo[2].RegClass == ARM::CCRRegClassID
> && "Exactly 3 operands expected");
>
> @@ -939,7 +939,7 @@
> const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
> if (!OpInfo) return false;
>
> - assert(NumOps == 1 && OpInfo[0].RegClass == 0 && "1 imm operand expected");
> + assert(NumOps == 1 && OpInfo[0].RegClass < 0 && "1 imm operand expected");
>
> unsigned Imm11 = getT1Imm11(insn);
>
> @@ -1239,7 +1239,7 @@
> && OpInfo[0].RegClass == ARM::GPRRegClassID
> && OpInfo[1].RegClass == ARM::GPRRegClassID
> && OpInfo[2].RegClass == ARM::GPRRegClassID
> - && OpInfo[3].RegClass == 0
> + && OpInfo[3].RegClass < 0
> && "Expect >= 4 operands and first 3 as reg operands");
>
> // Add the <Rt> <Rt2> operands.
> @@ -1322,8 +1322,8 @@
> assert(NumOps == 4
> && OpInfo[0].RegClass == ARM::GPRRegClassID
> && OpInfo[1].RegClass == ARM::GPRRegClassID
> - && OpInfo[2].RegClass == 0
> - && OpInfo[3].RegClass == 0
> + && OpInfo[2].RegClass < 0
> + && OpInfo[3].RegClass < 0
> && "Exactlt 4 operands expect and first two as reg operands");
> // Only need to populate the src reg operand.
> MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
> @@ -1375,7 +1375,7 @@
> if (NumOps == OpIdx)
> return true;
>
> - if (OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate()
> + if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
> && !OpInfo[OpIdx].isOptionalDef()) {
>
> if (Thumb2ShiftOpcode(Opcode))
> @@ -1440,7 +1440,7 @@
> }
>
> // The modified immediate operand should come next.
> - assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 &&
> + assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 &&
> !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
> && "Pure imm operand expected");
>
> @@ -1555,7 +1555,7 @@
> ++OpIdx;
> }
>
> - assert(OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate()
> + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
> && !OpInfo[OpIdx].isOptionalDef()
> && "Pure imm operand expected");
>
> @@ -1772,7 +1772,7 @@
> MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
> decodeRm(insn))));
> } else {
> - assert(OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate()
> + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
> && !OpInfo[OpIdx].isOptionalDef()
> && "Pure imm operand expected");
> int Offset = 0;
> @@ -1792,7 +1792,7 @@
> }
> ++OpIdx;
>
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 &&
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 &&
> !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> // Fills in the shift amount for t2PLDs, t2PLDWs, t2PLIs.
> MI.addOperand(MCOperand::CreateImm(slice(insn, 5, 4)));
> @@ -1818,7 +1818,7 @@
>
> assert(NumOps >= 2 &&
> OpInfo[0].RegClass == ARM::GPRRegClassID &&
> - OpInfo[1].RegClass == 0 &&
> + OpInfo[1].RegClass < 0 &&
> "Expect >= 2 operands, first as reg, and second as imm operand");
>
> // Build the register operand, followed by the (+/-)imm12 immediate.
> @@ -1930,7 +1930,7 @@
> ++OpIdx;
> }
>
> - assert(OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate()
> + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
> && !OpInfo[OpIdx].isOptionalDef()
> && "Pure imm operand expected");
>
> @@ -1981,7 +1981,7 @@
> decodeRm(insn))));
> ++OpIdx;
>
> - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0
> + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
> && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
> // Add the rotation amount immediate.
> MI.addOperand(MCOperand::CreateImm(decodeRotate(insn)));
>
> Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Fri Jun 18 13:13:55 2010
> @@ -28,6 +28,10 @@
> TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
> if (isLookupPtrRegClass())
> return TRI->getPointerRegClass(RegClass);
> + // Instructions like INSERT_SUBREG do not have fixed register classes.
> + if (RegClass < 0)
> + return 0;
> + // Otherwise just look it up normally.
> return TRI->getRegClass(RegClass);
> }
>
>
> Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Fri Jun 18 13:13:55 2010
> @@ -92,7 +92,8 @@
> else if (OpR->isSubClassOf("PointerLikeRegClass"))
> Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
> else
> - Res += "0, ";
> + // -1 means the operand does not have a fixed register class.
> + Res += "-1, ";
>
> // Fill in applicable flags.
> Res += "0";
>
> Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=106296&r1=106295&r2=106296&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 18 13:13:55 2010
> @@ -96,7 +96,7 @@
> for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
> if (i) OS << ",\n";
> OS << " " << RegisterClasses[i].getName() << "RegClassID";
> - OS << " = " << (i+1);
> + OS << " = " << i;
> }
> OS << "\n };\n\n";
>
>
>
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> llvm-commits at cs.uiuc.edu
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>
--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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