[llvm-commits] [llvm] r106152 - in /llvm/trunk: lib/CodeGen/LiveIntervalAnalysis.cpp test/CodeGen/Thumb2/crash.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Wed Jun 16 16:29:40 2010
New Revision: 106152

URL: http://llvm.org/viewvc/llvm-project?rev=106152&view=rev
Log:
Allow a register to be redefined multiple times in a basic block.

LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.

Here is an example of chained INSERT_SUBREGs that we can handle now:

68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                register: %reg1040 +[70,134:0)
76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0 at 78-(134) 1 at 70-(78)
84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0 at 86-(134) 1 at 70-(78) 2 at 78-(86)
92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0 at 94-(134) 1 at 70-(78) 2 at 78-(86) 3 at 86-(94)

rdar://problem/8096390

Added:
    llvm/trunk/test/CodeGen/Thumb2/crash.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=106152&r1=106151&r2=106152&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Jun 16 16:29:40 2010
@@ -434,11 +434,6 @@
       // are actually two values in the live interval.  Because of this we
       // need to take the LiveRegion that defines this register and split it
       // into two values.
-      // Two-address vregs should always only be redefined once.  This means
-      // that at this point, there should be exactly one value number in it.
-      assert((PartReDef || interval.containsOneValue()) &&
-             "Unexpected 2-addr liveint!");
-      SlotIndex DefIndex = interval.getValNumInfo(0)->def.getDefIndex();
       SlotIndex RedefIndex = MIIdx.getDefIndex();
       if (MO.isEarlyClobber())
         RedefIndex = MIIdx.getUseIndex();
@@ -446,8 +441,9 @@
       const LiveRange *OldLR =
         interval.getLiveRangeContaining(RedefIndex.getUseIndex());
       VNInfo *OldValNo = OldLR->valno;
+      SlotIndex DefIndex = OldValNo->def.getDefIndex();
 
-      // Delete the initial value, which should be short and continuous,
+      // Delete the previous value, which should be short and continuous,
       // because the 2-addr copy must be in the same MBB as the redef.
       interval.removeRange(DefIndex, RedefIndex);
 

Added: llvm/trunk/test/CodeGen/Thumb2/crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/crash.ll?rev=106152&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/crash.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/crash.ll Wed Jun 16 16:29:40 2010
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10"
+
+; This function would crash LiveIntervalAnalysis by creating a chain of 4 INSERT_SUBREGs of the same register.
+define arm_apcscc void @NEON_vst4q_u32(i32* nocapture %sp0, i32* nocapture %sp1, i32* nocapture %sp2, i32* nocapture %sp3, i32* %dp) nounwind {
+entry:
+  %0 = bitcast i32* %sp0 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
+  %1 = load <4 x i32>* %0, align 16               ; <<4 x i32>> [#uses=1]
+  %2 = bitcast i32* %sp1 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
+  %3 = load <4 x i32>* %2, align 16               ; <<4 x i32>> [#uses=1]
+  %4 = bitcast i32* %sp2 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
+  %5 = load <4 x i32>* %4, align 16               ; <<4 x i32>> [#uses=1]
+  %6 = bitcast i32* %sp3 to <4 x i32>*            ; <<4 x i32>*> [#uses=1]
+  %7 = load <4 x i32>* %6, align 16               ; <<4 x i32>> [#uses=1]
+  %8 = bitcast i32* %dp to i8*                    ; <i8*> [#uses=1]
+  tail call void @llvm.arm.neon.vst4.v4i32(i8* %8, <4 x i32> %1, <4 x i32> %3, <4 x i32> %5, <4 x i32> %7)
+  ret void
+}
+
+declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) nounwind