[llvm-commits] [llvm] r105722 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/vecinsert.ll
Kalle Raiskila
kalle.raiskila at nokia.com
Wed Jun 9 02:58:18 PDT 2010
Author: kraiskil
Date: Wed Jun 9 04:58:17 2010
New Revision: 105722
URL: http://llvm.org/viewvc/llvm-project?rev=105722&view=rev
Log:
Fix SPU to cope with vector insertelement to an undef position.
We default to inserting to lane 0.
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=105722&r1=105721&r2=105722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Jun 9 04:58:17 2010
@@ -2056,14 +2056,19 @@
DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType();
- ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
- assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
+ // use 0 when the lane to insert to is 'undef'
+ int64_t Idx=0;
+ if (IdxOp.getOpcode() != ISD::UNDEF) {
+ ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
+ assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
+ Idx = (CN->getSExtValue());
+ }
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $sp ($1) because it's always 16-byte aligned and it's available:
SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
- DAG.getConstant(CN->getSExtValue(), PtrVT));
+ DAG.getConstant(Idx, PtrVT));
SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
SDValue result =
Modified: llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll?rev=105722&r1=105721&r2=105722&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll Wed Jun 9 04:58:17 2010
@@ -1,17 +1,19 @@
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep cbd %t1.s | count 5
; RUN: grep chd %t1.s | count 5
-; RUN: grep cwd %t1.s | count 10
+; RUN: grep cwd %t1.s | count 11
; RUN: grep -w il %t1.s | count 5
; RUN: grep -w ilh %t1.s | count 6
; RUN: grep iohl %t1.s | count 1
; RUN: grep ilhu %t1.s | count 4
-; RUN: grep shufb %t1.s | count 26
+; RUN: grep shufb %t1.s | count 27
; RUN: grep 17219 %t1.s | count 1
; RUN: grep 22598 %t1.s | count 1
; RUN: grep -- -39 %t1.s | count 1
; RUN: grep 24 %t1.s | count 1
; RUN: grep 1159 %t1.s | count 1
+; RUN: FileCheck %s < %t1.s
+
; ModuleID = 'vecinsert.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
target triple = "spu-unknown-elf"
@@ -118,3 +120,12 @@
store <2 x double> %tmp3, <2 x double>* %arrayidx
ret void
}
+
+define <4 x i32> @undef_v4i32( i32 %param ) {
+ ;CHECK: cwd
+ ;CHECK: lqa
+ ;CHECK: shufb
+ %val = insertelement <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i32 %param, i32 undef
+ ret <4 x i32> %val
+}
+
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