[llvm-commits] [llvm] r105324 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp CriticalAntiDepBreaker.cpp

[Jim Grosbach]

Author: grosbach
Date: Wed Jun  2 10:29:36 2010
New Revision: 105324

URL: http://llvm.org/viewvc/llvm-project?rev=105324&view=rev
Log:
Not all entries in the range will have an SUnit. Check for that when looking
for debug information.

Modified:
    llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
    llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp

Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=105324&r1=105323&r2=105324&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Wed Jun  2 10:29:36 2010
@@ -909,6 +909,7 @@
               // information related to the anti-dependency register, make
               // sure to update that as well.
               const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()];
+              if (!SU) continue;
               for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) {
                 MachineInstr *DI = SU->DbgInstrList[i];
                 assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() &&

Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=105324&r1=105323&r2=105324&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Wed Jun  2 10:29:36 2010
@@ -530,6 +530,7 @@
           // related to the anti-dependency register, make sure to update that
           // as well.
           const SUnit *SU = MISUnitMap[Q->second->getParent()];
+          if (!SU) continue;
           for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) {
             MachineInstr *DI = SU->DbgInstrList[i];
             assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() &&