[llvm-commits] [llvm] r104904 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/Passes.cpp test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll test/CodeGen/X86/2008-05-21-CoalescerBug.ll test/CodeGen/X86/fast-isel-bc.ll test/CodeGen/X86/inline-asm-tied.ll
Jakob Stoklund Olesen
stoklund at 2pi.dk
Thu May 27 16:57:25 PDT 2010
Author: stoklund
Date: Thu May 27 18:57:25 2010
New Revision: 104904
URL: http://llvm.org/viewvc/llvm-project?rev=104904&view=rev
Log:
Add a -regalloc=default option that chooses a register allocator based on the -O
optimization level.
This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.
Modified:
llvm/trunk/include/llvm/CodeGen/Passes.h
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
llvm/trunk/lib/CodeGen/Passes.cpp
llvm/trunk/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll
llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
llvm/trunk/test/CodeGen/X86/fast-isel-bc.ll
llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll
Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=104904&r1=104903&r2=104904&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Thu May 27 18:57:25 2010
@@ -85,9 +85,10 @@
///
FunctionPass *createDeadMachineInstructionElimPass();
- /// Creates a register allocator as the user specified on the command line.
+ /// Creates a register allocator as the user specified on the command line, or
+ /// picks one that matches OptLevel.
///
- FunctionPass *createRegisterAllocator();
+ FunctionPass *createRegisterAllocator(CodeGenOpt::Level OptLevel);
/// LocalRegisterAllocation Pass - This pass register allocates the input code
/// a basic block at a time, yielding code better than the simple register
Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=104904&r1=104903&r2=104904&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu May 27 18:57:25 2010
@@ -358,7 +358,7 @@
/* allowDoubleDefs= */ true);
// Perform register allocation.
- PM.add(createRegisterAllocator());
+ PM.add(createRegisterAllocator(OptLevel));
printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring and post-ra machine LICM.
Modified: llvm/trunk/lib/CodeGen/Passes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=104904&r1=104903&r2=104904&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Passes.cpp (original)
+++ llvm/trunk/lib/CodeGen/Passes.cpp Thu May 27 18:57:25 2010
@@ -24,6 +24,11 @@
//===---------------------------------------------------------------------===//
MachinePassRegistry RegisterRegAlloc::Registry;
+static FunctionPass *createDefaultRegisterAllocator() { return 0; }
+static RegisterRegAlloc
+defaultRegAlloc("default",
+ "pick register allocator based on -O option",
+ createDefaultRegisterAllocator);
//===---------------------------------------------------------------------===//
///
@@ -33,8 +38,8 @@
static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
RegisterPassParser<RegisterRegAlloc> >
RegAlloc("regalloc",
- cl::init(&createLinearScanRegisterAllocator),
- cl::desc("Register allocator to use (default=linearscan)"));
+ cl::init(&createDefaultRegisterAllocator),
+ cl::desc("Register allocator to use"));
//===---------------------------------------------------------------------===//
@@ -42,13 +47,22 @@
/// createRegisterAllocator - choose the appropriate register allocator.
///
//===---------------------------------------------------------------------===//
-FunctionPass *llvm::createRegisterAllocator() {
+FunctionPass *llvm::createRegisterAllocator(CodeGenOpt::Level OptLevel) {
RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
-
+
if (!Ctor) {
Ctor = RegAlloc;
RegisterRegAlloc::setDefault(RegAlloc);
}
-
- return Ctor();
+
+ if (Ctor != createDefaultRegisterAllocator)
+ return Ctor();
+
+ // When the 'default' allocator is requested, pick one based on OptLevel.
+ switch (OptLevel) {
+ case CodeGenOpt::None:
+ return createLocalRegisterAllocator();
+ default:
+ return createLinearScanRegisterAllocator();
+ }
}
Modified: llvm/trunk/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll?rev=104904&r1=104903&r2=104904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll Thu May 27 18:57:25 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon -O0
+; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=linearscan
; This test would crash the rewriter when trying to handle a spill after one of
; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register.
Modified: llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll?rev=104904&r1=104903&r2=104904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll Thu May 27 18:57:25 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -O0 -fast-isel=false | grep mov | count 5
+; RUN: llc < %s -march=x86 -O0 -fast-isel=false -regalloc=linearscan | grep mov | count 5
; PR2343
%llvm.dbg.anchor.type = type { i32, i32 }
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-bc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bc.ll?rev=104904&r1=104903&r2=104904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-bc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-bc.ll Thu May 27 18:57:25 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
+; RUN: llc < %s -O0 -regalloc=linearscan -march=x86-64 -mattr=+mmx | FileCheck %s
; PR4684
target datalayout =
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll?rev=104904&r1=104903&r2=104904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll Thu May 27 18:57:25 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 12(%esp)} | count 2
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl %edx, 12(%esp)} | count 2
; rdar://6992609
target triple = "i386-apple-darwin9.0"
More information about the llvm-commits
mailing list