[llvm-commits] [llvm] r104615 - in /llvm/trunk: lib/Target/X86/X86RegisterInfo.cpp utils/TableGen/CodeGenTarget.h utils/TableGen/RegisterInfoEmitter.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Tue May 25 10:21:05 PDT 2010
Author: stoklund
Date: Tue May 25 12:21:04 2010
New Revision: 104615
URL: http://llvm.org/viewvc/llvm-project?rev=104615&view=rev
Log:
Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.
Then I'll remove NumberHack entirely.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.h
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=104615&r1=104614&r2=104615&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue May 25 12:21:04 2010
@@ -158,7 +158,7 @@
switch (SubIdx) {
default: return 0;
case X86::sub_8bit:
- //case X86::sub_ss:
+ case X86::sub_ss:
if (B == &X86::GR8RegClass) {
if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
return A;
@@ -195,7 +195,7 @@
}
break;
case X86::sub_8bit_hi:
- //case X86::sub_sd:
+ case X86::sub_sd:
if (B == &X86::GR8_ABCD_HRegClass) {
if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
A == &X86::GR64_NOREXRegClass ||
@@ -213,7 +213,7 @@
}
break;
case X86::sub_16bit:
- //case X86::sub_xmm:
+ case X86::sub_xmm:
if (B == &X86::GR16RegClass) {
if (A->getSize() == 4 || A->getSize() == 8)
return A;
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=104615&r1=104614&r2=104615&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.h Tue May 25 12:21:04 2010
@@ -107,7 +107,11 @@
// Map a SubRegIndex Record to its number.
unsigned getSubRegIndexNo(Record *idx) const {
- return idx->getValueAsInt("NumberHack");
+ if (SubRegIndices.empty()) ReadSubRegIndices();
+ std::vector<Record*>::const_iterator i =
+ std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
+ assert(i != SubRegIndices.end() && "Not a SubRegIndex");
+ return (i - SubRegIndices.begin()) + 1;
}
const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=104615&r1=104614&r2=104615&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue May 25 12:21:04 2010
@@ -52,8 +52,7 @@
OS << "namespace " << Namespace << " {\n";
OS << "enum {\n NoSubRegister,\n";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
- OS << " " << SubRegIndices[i]->getName() << " = "
- << SubRegIndices[i]->getValueAsInt("NumberHack") << ",\n";
+ OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n";
OS << "};\n";
if (!Namespace.empty())
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