[llvm-commits] [llvm] r103749 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Evan Cheng evan.cheng at apple.com
Thu May 13 17:21:45 PDT 2010


Author: evancheng
Date: Thu May 13 19:21:45 2010
New Revision: 103749

URL: http://llvm.org/viewvc/llvm-project?rev=103749&view=rev
Log:
Fix comments.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=103749&r1=103748&r2=103749&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu May 13 19:21:45 2010
@@ -968,7 +968,7 @@
                                 VT, SDValue(Pair, 0), V1, SubReg1);
 }
 
-/// PairDRegs - Form a quad register pair from a pair of Q registers.
+/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
 ///
 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
   DebugLoc dl = V0.getNode()->getDebugLoc();
@@ -978,7 +978,7 @@
   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
 }
 
-/// QuadDRegs - Form a octo register from a quad of D registers.
+/// QuadDRegs - Form 4 consecutive D registers.
 ///
 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
                                    SDValue V2, SDValue V3) {





More information about the llvm-commits mailing list