[llvm-commits] [llvm] r103684 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

[Evan Cheng]

Author: evancheng
Date: Wed May 12 19:17:02 2010
New Revision: 103684

URL: http://llvm.org/viewvc/llvm-project?rev=103684&view=rev
Log:
Expand VMOVQQ into a pair of VMOVQ.

Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=103684&r1=103683&r2=103684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed May 12 19:17:02 2010
@@ -29,6 +29,7 @@
     ARMExpandPseudo() : MachineFunctionPass(&ID) {}
 
     const TargetInstrInfo *TII;
+    const TargetRegisterInfo *TRI;
 
     virtual bool runOnMachineFunction(MachineFunction &Fn);
 
@@ -128,6 +129,31 @@
       TransferImpOps(MI, LO16, HI16);
       MI.eraseFromParent();
       Modified = true;
+      break;
+    }
+
+    case ARM::VMOVQQ: {
+      unsigned DstReg = MI.getOperand(0).getReg();
+      bool DstIsDead = MI.getOperand(0).isDead();
+      unsigned EvenDst = TRI->getSubReg(DstReg, ARM::QSUBREG_0);
+      unsigned OddDst  = TRI->getSubReg(DstReg, ARM::QSUBREG_1);
+      unsigned SrcReg = MI.getOperand(1).getReg();
+      bool SrcIsKill = MI.getOperand(1).isKill();
+      unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::QSUBREG_0);
+      unsigned OddSrc  = TRI->getSubReg(SrcReg, ARM::QSUBREG_1);
+      MachineInstrBuilder Even =
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                               TII->get(ARM::VMOVQ))
+                       .addReg(EvenDst, getDefRegState(true) | getDeadRegState(DstIsDead))
+                       .addReg(EvenSrc, getKillRegState(SrcIsKill)));
+      MachineInstrBuilder Odd =
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                               TII->get(ARM::VMOVQ))
+                       .addReg(OddDst, getDefRegState(true) | getDeadRegState(DstIsDead))
+                       .addReg(OddSrc, getKillRegState(SrcIsKill)));
+      TransferImpOps(MI, Even, Odd);
+      MI.eraseFromParent();
+      Modified = true;
     }
     }
     MBBI = NMBBI;
@@ -138,6 +164,7 @@
 
 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
   TII = MF.getTarget().getInstrInfo();
+  TRI = MF.getTarget().getRegisterInfo();
 
   bool Modified = false;
   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;