[llvm-commits] [llvm] r103466 - in /llvm/trunk: lib/Target/CellSPU/SPUInstrInfo.cpp test/CodeGen/CellSPU/jumptable.ll

[Kalle Raiskila]

Author: kraiskil
Date: Tue May 11 06:00:02 2010
New Revision: 103466

URL: http://llvm.org/viewvc/llvm-project?rev=103466&view=rev
Log:
Make SPU backend not assert on jump tables.

Added:
    llvm/trunk/test/CodeGen/CellSPU/jumptable.ll
Modified:
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=103466&r1=103465&r2=103466&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Tue May 11 06:00:02 2010
@@ -467,6 +467,9 @@
   // If there is only one terminator instruction, process it.
   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
     if (isUncondBranch(LastInst)) {
+      // Check for jump tables
+      if (!LastInst->getOperand(0).isMBB())
+        return true;
       TBB = LastInst->getOperand(0).getMBB();
       return false;
     } else if (isCondBranch(LastInst)) {

Added: llvm/trunk/test/CodeGen/CellSPU/jumptable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/jumptable.ll?rev=103466&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/jumptable.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/jumptable.ll Tue May 11 06:00:02 2010
@@ -0,0 +1,21 @@
+;RUN: llc --march=cellspu %s -o - | FileCheck %s
+; This is to check that emitting jumptables doesn't crash llc
+define i32 @test(i32 %param) {
+entry:
+;CHECK:        ai      $4, $3, -1
+;CHECK:        clgti   $5, $4, 3
+;CHECK:        brnz    $5,.LBB0_2
+  switch i32 %param, label %bb1 [
+    i32 1, label %bb3
+    i32 2, label %bb2
+    i32 3, label %bb3
+    i32 4, label %bb1
+  ]
+
+bb1:                                            
+  ret i32 1
+bb2:      
+  ret i32 2
+bb3:     
+  ret i32 3
+}