[llvm-commits] [llvm] r103277 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/Thumb2/sign_extend_inreg.ll

[Jim Grosbach]

Author: grosbach
Date: Fri May  7 13:34:55 2010
New Revision: 103277

URL: http://llvm.org/viewvc/llvm-project?rev=103277&view=rev
Log:
Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.

rdar://7956878


Added:
    llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=103277&r1=103276&r2=103277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri May  7 13:34:55 2010
@@ -393,8 +393,11 @@
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
   setOperationAction(ISD::MEMBARRIER,         MVT::Other, Custom);
 
-  if (!Subtarget->hasV6Ops() && (!Subtarget->isThumb2()
-      || !Subtarget->hasT2ExtractPack())) {
+  // If the subtarget does not have extract instructions, sign_extend_inreg
+  // needs to be expanded. Extract is available in ARM mode on v6 and up,
+  // and on most Thumb2 implementations.
+  if ((!Subtarget->isThumb() && !Subtarget->hasV6Ops())
+      || (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
   }

Added: llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll?rev=103277&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll Fri May  7 13:34:55 2010
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-A8
+; RUN: llc < %s -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK-M3
+
+target triple = "thumbv7-apple-darwin10"
+
+define arm_apcscc i32 @f1(i16* %ptr) nounwind {
+; CHECK-A8: f1
+; CHECK-A8: sxth
+; CHECK-M3: f1
+; CHECK-M3-NOT: sxth
+; CHECK-M3: bx lr
+  %1 = load i16* %ptr
+  %2 = icmp eq i16 %1, 1
+  %3 = sext i16 %1 to i32
+  br i1 %2, label %.next, label %.exit
+
+.next:
+  br label %.exit
+
+.exit:
+  ret i32 %3
+}