[llvm-commits] [llvm] r103159 - in /llvm/trunk/lib/Target: ARM/ARMBaseInstrInfo.cpp ARM/ARMBaseRegisterInfo.cpp ARM/ARMInstrNEON.td ARM/ARMRegisterInfo.h ARM/ARMRegisterInfo.td X86/X86RegisterInfo.cpp
Eric Christopher
echristo at apple.com
Wed May 5 19:29:06 PDT 2010
Author: echristo
Date: Wed May 5 21:29:06 2010
New Revision: 103159
URL: http://llvm.org/viewvc/llvm-project?rev=103159&view=rev
Log:
Revert r103156 since it was breaking the build bots.
Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=103159&r1=103158&r2=103159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed May 5 21:29:06 2010
@@ -545,8 +545,7 @@
case ARM::VMOVS:
case ARM::VMOVD:
case ARM::VMOVDneon:
- case ARM::VMOVQ:
- case ARM::VMOVQQ : {
+ case ARM::VMOVQ: {
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
SrcSubIdx = MI.getOperand(1).getSubReg();
@@ -682,14 +681,6 @@
SrcRC == ARM::QPR_8RegisterClass)
SrcRC = ARM::QPRRegisterClass;
- // Allow QQPR / QQPR_VFP2 / QQPR_8 cross-class copies.
- if (DestRC == ARM::QQPR_VFP2RegisterClass ||
- DestRC == ARM::QQPR_8RegisterClass)
- DestRC = ARM::QQPRRegisterClass;
- if (SrcRC == ARM::QQPR_VFP2RegisterClass ||
- SrcRC == ARM::QQPR_8RegisterClass)
- SrcRC = ARM::QQPRRegisterClass;
-
// Disallow copies of unequal sizes.
if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
return false;
@@ -714,12 +705,11 @@
Opc = ARM::VMOVDneon;
else if (DestRC == ARM::QPRRegisterClass)
Opc = ARM::VMOVQ;
- else if (DestRC == ARM::QQPRRegisterClass)
- Opc = ARM::VMOVQQ;
else
return false;
- AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg));
+ AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
+ .addReg(SrcReg));
}
return true;
@@ -760,11 +750,12 @@
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
- } else if (RC == ARM::QPRRegisterClass ||
- RC == ARM::QPR_VFP2RegisterClass ||
- RC == ARM::QPR_8RegisterClass) {
+ } else {
+ assert((RC == ARM::QPRRegisterClass ||
+ RC == ARM::QPR_VFP2RegisterClass ||
+ RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates
- if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+ if (Align >= 16 && (getRegisterInfo().canRealignStack(MF))) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
.addFrameIndex(FI).addImm(128)
.addMemOperand(MMO)
@@ -776,11 +767,6 @@
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
.addMemOperand(MMO));
}
- } else {
- assert((RC == ARM::QQPRRegisterClass ||
- RC == ARM::QQPR_VFP2RegisterClass ||
- RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
- llvm_unreachable("Not yet implemented!");
}
}
@@ -816,10 +802,12 @@
RC == ARM::DPR_8RegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
- } else if (RC == ARM::QPRRegisterClass ||
- RC == ARM::QPR_VFP2RegisterClass ||
- RC == ARM::QPR_8RegisterClass) {
- if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+ } else {
+ assert((RC == ARM::QPRRegisterClass ||
+ RC == ARM::QPR_VFP2RegisterClass ||
+ RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
+ if (Align >= 16
+ && (getRegisterInfo().canRealignStack(MF))) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
.addFrameIndex(FI).addImm(128)
.addMemOperand(MMO));
@@ -829,11 +817,6 @@
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
.addMemOperand(MMO));
}
- } else {
- assert((RC == ARM::QQPRRegisterClass ||
- RC == ARM::QQPR_VFP2RegisterClass ||
- RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
- llvm_unreachable("Not yet implemented!");
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=103159&r1=103158&r2=103159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed May 5 21:29:06 2010
@@ -262,7 +262,7 @@
case 1:
case 2:
case 3:
- case 4: {
+ case 4:
// S sub-registers.
if (A->getSize() == 8) {
if (B == &ARM::SPR_8RegClass)
@@ -273,48 +273,19 @@
return &ARM::DPR_VFP2RegClass;
}
- if (A->getSize() == 16) {
- if (B == &ARM::SPR_8RegClass)
- return &ARM::QPR_8RegClass;
- return &ARM::QPR_VFP2RegClass;
- }
-
- assert(A->getSize() == 32 && "Expecting a QQ register class!");
+ assert(A->getSize() == 16 && "Expecting a Q register class!");
if (B == &ARM::SPR_8RegClass)
- return &ARM::QQPR_8RegClass;
- return &ARM::QQPR_VFP2RegClass;
- }
+ return &ARM::QPR_8RegClass;
+ return &ARM::QPR_VFP2RegClass;
case 5:
case 6:
- case 7:
- case 8: {
// D sub-registers.
- if (A->getSize() == 16) {
- if (B == &ARM::DPR_VFP2RegClass)
- return &ARM::QPR_VFP2RegClass;
- if (B == &ARM::DPR_8RegClass)
- return &ARM::QPR_8RegClass;
- return A;
- }
-
- assert(A->getSize() == 32 && "Expecting a QQ register class!");
if (B == &ARM::DPR_VFP2RegClass)
- return &ARM::QQPR_VFP2RegClass;
+ return &ARM::QPR_VFP2RegClass;
if (B == &ARM::DPR_8RegClass)
- return &ARM::QQPR_8RegClass;
+ return &ARM::QPR_8RegClass;
return A;
}
- case 9:
- case 10: {
- // Q sub-registers.
- assert(A->getSize() == 32 && "Expecting a QQ register class!");
- if (B == &ARM::QPR_VFP2RegClass)
- return &ARM::QQPR_VFP2RegClass;
- if (B == &ARM::QPR_8RegClass)
- return &ARM::QQPR_8RegClass;
- return A;
- }
- }
return 0;
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=103159&r1=103158&r2=103159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed May 5 21:29:06 2010
@@ -2834,11 +2834,6 @@
def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
-// Pseudo vector move instruction for QQ (a pair of Q) registers. This should
-// be expanded after register allocation is completed.
-def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
- NoItinerary, "@ vmov\t$dst, $src", []>;
-
// VMOV : Vector Move (Immediate)
// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h?rev=103159&r1=103158&r2=103159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Wed May 5 21:29:06 2010
@@ -29,8 +29,7 @@
/// ARMRegisterInfo.td file.
enum SubregIndex {
SSUBREG_0 = 1, SSUBREG_1 = 2, SSUBREG_2 = 3, SSUBREG_3 = 4,
- DSUBREG_0 = 5, DSUBREG_1 = 6, DSUBREG_2 = 7, DSUBREG_3 = 8,
- QSUBREG_0 = 9, QSUBREG_1 = 10
+ DSUBREG_0 = 5, DSUBREG_1 = 6
};
}
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=103159&r1=103158&r2=103159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Wed May 5 21:29:06 2010
@@ -106,17 +106,6 @@
def Q14 : ARMReg<14, "q14", [D28, D29]>;
def Q15 : ARMReg<15, "q15", [D30, D31]>;
-// Pseudo 256-bit registers to represent pairs of Q registers. These should
-// never be present in the emitted code.
-def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>;
-def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>;
-def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>;
-def QQ3 : ARMReg<3, "qq3", [Q6, Q7]>;
-def QQ4 : ARMReg<4, "qq4", [Q8, Q9]>;
-def QQ5 : ARMReg<5, "qq5", [Q10, Q11]>;
-def QQ6 : ARMReg<6, "qq6", [Q12, Q13]>;
-def QQ7 : ARMReg<7, "qq7", [Q14, Q15]>;
-
// Current Program Status Register.
def CPSR : ARMReg<0, "cpsr">;
@@ -375,32 +364,6 @@
let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8, DPR_8, DPR_8];
}
-// Pseudo 256-bit vector register class to model pairs of Q registers.
-def QQPR : RegisterClass<"ARM", [v4i64],
- 256,
- [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7]> {
- let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
- DPR, DPR, DPR, DPR, QPR, QPR];
-}
-
-// Subset of QQPR that have 32-bit SPR subregs.
-def QQPR_VFP2 : RegisterClass<"ARM", [v4i64],
- 256,
- [QQ0, QQ1, QQ2, QQ3]> {
- let SubRegClassList = [SPR, SPR, SPR, SPR,
- DPR_VFP2, DPR_VFP2, DPR_VFP2, DPR_VFP2,
- QPR_VFP2, QPR_VFP2];
-}
-
-// Subset of QQPR that have QPR_8, DPR_8, and SPR_8 subregs.
-def QQPR_8 : RegisterClass<"ARM", [v4i64],
- 256,
- [QQ0, QQ1]> {
- let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8,
- DPR_8, DPR_8, DPR_8, DPR_8,
- QPR_8, QPR_8];
-}
-
// Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
@@ -415,10 +378,6 @@
def arm_ssubreg_3 : PatLeaf<(i32 4)>;
def arm_dsubreg_0 : PatLeaf<(i32 5)>;
def arm_dsubreg_1 : PatLeaf<(i32 6)>;
-def arm_dsubreg_2 : PatLeaf<(i32 7)>;
-def arm_dsubreg_3 : PatLeaf<(i32 8)>;
-def arm_qsubreg_0 : PatLeaf<(i32 9)>;
-def arm_qsubreg_1 : PatLeaf<(i32 10)>;
// S sub-registers of D registers.
def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
@@ -449,31 +408,3 @@
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
[D1, D3, D5, D7, D9, D11, D13, D15,
D17, D19, D21, D23, D25, D27, D29, D31]>;
-
-// S sub-registers of QQ registers. Note there are no sub-indices
-// for referencing S4 - S7, S12 - S15, and S20 - S23. It doesn't
-// look like we need them.
-def : SubRegSet<1, [QQ0, QQ1, QQ2, QQ3],
- [S0, S8, S16, S24]>;
-def : SubRegSet<2, [QQ0, QQ1, QQ2, QQ3],
- [S1, S9, S17, S25]>;
-def : SubRegSet<3, [QQ0, QQ1, QQ2, QQ3],
- [S2, S10, S18, S26]>;
-def : SubRegSet<4, [QQ0, QQ1, QQ2, QQ3],
- [S3, S11, S19, S27]>;
-
-// D sub-registers of QQ registers.
-def : SubRegSet<5, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D0, D4, D8, D12, D16, D20, D24, D28]>;
-def : SubRegSet<6, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D1, D5, D9, D13, D17, D21, D25, D29]>;
-def : SubRegSet<7, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D2, D6, D10, D14, D18, D22, D26, D30]>;
-def : SubRegSet<8, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [D3, D7, D11, D15, D19, D23, D27, D31]>;
-
-// Q sub-registers of QQ registers.
-def : SubRegSet<9, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14]>;
-def : SubRegSet<10,[QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
- [Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15]>;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=103159&r1=103158&r2=103159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed May 5 21:29:06 2010
@@ -716,7 +716,7 @@
void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
unsigned StackPtr, uint64_t *NumBytes = NULL) {
if (MBBI == MBB.begin()) return;
-
+
MachineBasicBlock::iterator PI = prior(MBBI);
unsigned Opc = PI->getOpcode();
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
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