[llvm-commits] [llvm] r102838 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
Anton Korobeynikov
asl at math.spbu.ru
Sat May 1 05:52:35 PDT 2010
Author: asl
Date: Sat May 1 07:52:34 2010
New Revision: 102838
URL: http://llvm.org/viewvc/llvm-project?rev=102838&view=rev
Log:
Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),
when needed. This fixes PR7001
Added:
llvm/trunk/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=102838&r1=102837&r2=102838&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat May 1 07:52:34 2010
@@ -1882,10 +1882,15 @@
isa<ConstantSDNode>(Op0.getOperand(1)) &&
cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
- if (Op0.getValueType() != VT)
+ if (Op0.getValueType().bitsGT(VT))
Op0 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
DAG.getConstant(1, VT));
+ else if (Op0.getValueType().bitsLT(VT))
+ Op0 = DAG.getNode(ISD::AND, dl, VT,
+ DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
+ DAG.getConstant(1, VT));
+
return DAG.getSetCC(dl, VT, Op0,
DAG.getConstant(0, Op0.getValueType()),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
Added: llvm/trunk/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll?rev=102838&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll (added)
+++ llvm/trunk/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll Sat May 1 07:52:34 2010
@@ -0,0 +1,27 @@
+; RUN: llc < %s
+; PR7001
+
+target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
+target triple = "msp430-elf"
+
+define i16 @main() nounwind {
+entry:
+ br label %while.cond
+
+while.cond: ; preds = %while.body, %entry
+ br i1 undef, label %land.rhs, label %land.end
+
+land.rhs: ; preds = %while.cond
+ br label %land.end
+
+land.end: ; preds = %land.rhs, %while.cond
+ %0 = phi i1 [ false, %while.cond ], [ undef, %land.rhs ] ; <i1> [#uses=1]
+ br i1 %0, label %while.body, label %while.end
+
+while.body: ; preds = %land.end
+ %tmp4 = load i16* undef ; <i16> [#uses=0]
+ br label %while.cond
+
+while.end: ; preds = %land.end
+ ret i16 undef
+}
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