[llvm-commits] [llvm] r102492 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Evan Cheng]

Author: evancheng
Date: Wed Apr 28 02:10:39 2010
New Revision: 102492

URL: http://llvm.org/viewvc/llvm-project?rev=102492&view=rev
Log:
Try operation promotion only if regular dag combine and target-specific ones failed to do anything.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=102492&r1=102491&r2=102492&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 28 02:10:39 2010
@@ -1011,7 +1011,7 @@
 }
 
 SDValue DAGCombiner::visit(SDNode *N) {
-  switch(N->getOpcode()) {
+  switch (N->getOpcode()) {
   default: break;
   case ISD::TokenFactor:        return visitTokenFactor(N);
   case ISD::MERGE_VALUES:       return visitMERGE_VALUES(N);
@@ -1096,6 +1096,35 @@
     }
   }
 
+  // If nothing happened still, try promoting the operation.
+  if (RV.getNode() == 0) {
+    switch (N->getOpcode()) {
+    default: break;
+    case ISD::ADD:
+    case ISD::SUB:
+    case ISD::MUL:
+    case ISD::AND:
+    case ISD::OR:
+    case ISD::XOR:
+      RV = PromoteIntBinOp(SDValue(N, 0));
+      break;
+    case ISD::SHL:
+    case ISD::SRA:
+    case ISD::SRL:
+      RV = PromoteIntShiftOp(SDValue(N, 0));
+      break;
+    case ISD::SIGN_EXTEND:
+    case ISD::ZERO_EXTEND:
+    case ISD::ANY_EXTEND:
+      RV = PromoteExtend(SDValue(N, 0));
+      break;
+    case ISD::LOAD:
+      if (PromoteLoad(SDValue(N, 0)))
+        RV = SDValue(N, 0);
+      break;
+    }
+  }
+
   // If N is a commutative binary node, try commuting it to enable more
   // sdisel CSE.
   if (RV.getNode() == 0 &&
@@ -1387,7 +1416,7 @@
                                        N0.getOperand(0).getOperand(1),
                                        N0.getOperand(1)));
 
-  return PromoteIntBinOp(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitADDC(SDNode *N) {
@@ -1525,7 +1554,7 @@
                                  VT);
     }
 
-  return PromoteIntBinOp(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitMUL(SDNode *N) {
@@ -1618,7 +1647,7 @@
   if (RMUL.getNode() != 0)
     return RMUL;
 
-  return PromoteIntBinOp(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitSDIV(SDNode *N) {
@@ -2264,7 +2293,7 @@
     }
   }
 
-  return PromoteIntBinOp(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitOR(SDNode *N) {
@@ -2390,7 +2419,7 @@
   if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
     return SDValue(Rot, 0);
 
-  return PromoteIntBinOp(SDValue(N, 0));
+  return SDValue();
 }
 
 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
@@ -2699,7 +2728,7 @@
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
 
-  return PromoteIntBinOp(SDValue(N, 0));
+  return SDValue();
 }
 
 /// visitShiftByConstant - Handle transforms common to the three shifts, when
@@ -2866,7 +2895,7 @@
       return NewSHL;
   }
 
-  return PromoteIntShiftOp(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitSRA(SDNode *N) {
@@ -2986,7 +3015,7 @@
       return NewSRA;
   }
 
-  return PromoteIntShiftOp(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitSRL(SDNode *N) {
@@ -3152,7 +3181,7 @@
     }
   }
 
-  return PromoteIntShiftOp(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
@@ -3550,7 +3579,7 @@
       DAG.SignBitIsZero(N0))
     return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
 
-  return PromoteExtend(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
@@ -3713,7 +3742,7 @@
                                    N0.getOperand(1)));
   }
 
-  return PromoteExtend(SDValue(N, 0));
+  return SDValue();
 }
 
 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
@@ -3849,7 +3878,7 @@
       return SCC;
   }
 
-  return PromoteExtend(SDValue(N, 0));
+  return SDValue();
 }
 
 /// GetDemandedBits - See if the specified operand can be simplified with the
@@ -5451,8 +5480,6 @@
   if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
     return SDValue(N, 0);
 
-  if (PromoteLoad(SDValue(N, 0)))
-    return SDValue(N, 0);
   return SDValue();
 }