[llvm-commits] Fix for assertion in DAGCombiner

[Dan Gohman]

On Apr 24, 2010, at 7:42 AM, Jan Sjodin wrote:

> 
> 
>> On x86, support for vector SETCC is currently limited to cases where the
>> result is sign-extended to a vector of the same width as the SETCC 
>> operand vector. In other words, if you change the <3 x i32> to <3 x 
>> i64 here it'll work, because i64 is the same width as double.
>> 
>> Dan
> 
> That is unfortunate. Is conversion from a vector to another of smaller size
> supported? It might be possible to sign extend to i64, then convert to i32.
> Even if the support is direct, the code generation will have to do something
> like this anyway.

The IR supports this for its part, but overall, this is relatively new
territory for LLVM in general. If you find things that don't work, bugs
and patches are welcome.

Dan