[llvm-commits] Fix for assertion in DAGCombiner

[Dan Gohman]

On Apr 23, 2010, at 9:41 AM, Jan Sjodin wrote:

> Small fix that prevents an assertion in getConstant if VT is a vector type.
> 
> Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> ===================================================================
> --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp    (revision 102107)
> +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp    (working copy)
> @@ -3453,7 +3453,8 @@
> 
>     // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
>     SDValue NegOne =
> -      DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
> +      DAG.getConstant(APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()),
> +                     VT);
>     SDValue SCC =
>       SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
>                        NegOne, DAG.getConstant(0, VT),

Thanks! This is now applied (with a trivial edit for 80 columns).

> 
> I was going to use the example below, but there are still more errors to be fixed (see below):
> 
> ; ModuleID = 'minimal.bc'
> target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:6\
> 4:64-f80:128:128"
> target triple = "x86_64-pc-linux-gnu"
> 
> define void @myfunction(<3 x double>* %foo, <3 x double>* %bar, <3 x i32>* %result) {
> entry:
>  %foo.value = load <3 x double>* %foo            ; <<3 x double>> [#uses=1]
>  %bar.value = load <3 x double>* %bar            ; <<3 x double>> [#uses=1]
>  %cmp.i.i = fcmp oeq <3 x double> %foo.value, %bar.value ; <<3 x i1>> [#uses=1]
>  %cmp.ext.i.i = sext <3 x i1> %cmp.i.i to <3 x i32> ; <<3 x i32>> [#uses=1]
>  store <3 x i32> %cmp.ext.i.i, <3 x i32>* %result
>  ret void
> }
> 
> 
> llc fails:
> WidenVectorOperand op #0: 0xb7fc520: i8 = setcc 0xb7fbe38, 0xb7fbec0, 0xb7fbf48
> [ID=0]
> Do not know how to widen this operator's operand!
> UNREACHABLE executed at LegalizeVectorTypes.cpp:1898!
> 
> I will try and look into this as well.

On x86, support for vector SETCC is currently limited to cases where the
result is sign-extended to a vector of the same width as the SETCC operand
vector. In other words, if you change the <3 x i32> to <3 x i64> here 
it'll work, because i64 is the same width as double.

Dan