[llvm-commits] [llvm] r100899 - in /llvm/trunk/utils/TableGen: ARMDecoderEmitter.cpp Record.h

[Johnny Chen]

Author: johnny
Date: Fri Apr  9 16:01:02 2010
New Revision: 100899

URL: http://llvm.org/viewvc/llvm-project?rev=100899&view=rev
Log:
If all the bit positions are not specified; do not decode the instructions.
We are bound to fail!  For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.

This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.

Modified:
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
    llvm/trunk/utils/TableGen/Record.h

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=100899&r1=100898&r2=100899&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Fri Apr  9 16:01:02 2010
@@ -1550,6 +1550,16 @@
   const StringRef Name = Def.getName();
   uint8_t Form = getByteField(Def, "Form");
 
+  BitsInit &Bits = getBitsField(Def, "Inst");
+
+  // If all the bit positions are not specified; do not decode this instruction.
+  // We are bound to fail!  For proper disassembly, the well-known encoding bits
+  // of the instruction must be fully specified.
+  //
+  // This also removes pseudo instructions from considerations of disassembly,
+  // which is a better design and less fragile than the name matchings.
+  if (Bits.allInComplete()) return false;
+
   if (TN == TARGET_ARM) {
     // FIXME: what about Int_MemBarrierV6 and Int_SyncBarrierV6?
     if ((Name != "Int_MemBarrierV7" && Name != "Int_SyncBarrierV7") &&
@@ -1670,13 +1680,6 @@
     if (!thumbInstruction(Form))
       return false;
 
-    // Ignore pseudo instructions.
-    if (Name == "tInt_eh_sjlj_setjmp" || Name == "t2Int_eh_sjlj_setjmp" ||
-        Name == "tInt_eh_sjlj_setjmp_nofp" ||
-        Name == "t2Int_eh_sjlj_setjmp_nofp" ||
-        Name == "t2MOVi32imm" || Name == "tBX" || Name == "tBXr9")
-      return false;
-
     // On Darwin R9 is call-clobbered.  Ignore the non-Darwin counterparts.
     if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr")
       return false;
@@ -1741,8 +1744,6 @@
   }
 
   DEBUG({
-      BitsInit &Bits = getBitsField(Def, "Inst");
-
       errs() << " ";
 
       // Dumps the instruction encoding bits.

Modified: llvm/trunk/utils/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=100899&r1=100898&r2=100899&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.h (original)
+++ llvm/trunk/utils/TableGen/Record.h Fri Apr  9 16:01:02 2010
@@ -609,6 +609,11 @@
       if (!getBit(i)->isComplete()) return false;
     return true;
   }
+  bool allInComplete() const {
+    for (unsigned i = 0; i != getNumBits(); ++i)
+      if (getBit(i)->isComplete()) return false;
+    return true;
+  }
   virtual std::string getAsString() const;
 
   virtual Init *resolveReferences(Record &R, const RecordVal *RV);