[llvm-commits] [llvm] r100767 - in /llvm/trunk: lib/MC/MachObjectWriter.cpp lib/Support/regengine.inc utils/TableGen/ARMDecoderEmitter.cpp

[Benjamin Kramer]

Author: d0k
Date: Thu Apr  8 10:25:57 2010
New Revision: 100767

URL: http://llvm.org/viewvc/llvm-project?rev=100767&view=rev
Log:
Various MSVC warning fixes about truncated 64 bit shifts and const pointers passed to free.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/Support/regengine.inc
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=100767&r1=100766&r2=100767&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Apr  8 10:25:57 2010
@@ -477,7 +477,7 @@
       // actual expression addend without the PCrel bias. However, instructions
       // with data following the relocation are not accomodated for (see comment
       // below regarding SIGNED{1,2,4}), so it isn't exactly that either.
-      Value += 1 << Log2Size;
+      Value += 1LL << Log2Size;
     }
 
     if (Target.isAbsolute()) { // constant
@@ -605,7 +605,7 @@
         // well based on the actual encoded instruction (the additional bias),
         // but instead appear to just look at the final offset.
         if (IsRIPRel) {
-          switch (-(Target.getConstant() + (1 << Log2Size))) {
+          switch (-(Target.getConstant() + (1LL << Log2Size))) {
           case 1: Type = RIT_X86_64_Signed1; break;
           case 2: Type = RIT_X86_64_Signed2; break;
           case 4: Type = RIT_X86_64_Signed4; break;

Modified: llvm/trunk/lib/Support/regengine.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/regengine.inc?rev=100767&r1=100766&r2=100767&view=diff
==============================================================================
--- llvm/trunk/lib/Support/regengine.inc (original)
+++ llvm/trunk/lib/Support/regengine.inc Thu Apr  8 10:25:57 2010
@@ -185,7 +185,7 @@
 		endp = fast(m, start, stop, gf, gl);
 		if (endp == NULL) {		/* a miss */
 			free(m->pmatch);
-			free(m->lastpos);
+			free((void*)m->lastpos);
 			STATETEARDOWN(m);
 			return(REG_NOMATCH);
 		}

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=100767&r1=100766&r2=100767&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Thu Apr  8 10:25:57 2010
@@ -635,7 +635,7 @@
 
     // Marks all the segment positions with either BIT_TRUE or BIT_FALSE.
     for (bitIndex = 0; bitIndex < NumBits; bitIndex++) {
-      if (mapIterator->first & (1 << bitIndex))
+      if (mapIterator->first & (1ULL << bitIndex))
         BitValueArray[StartBit + bitIndex] = BIT_TRUE;
       else
         BitValueArray[StartBit + bitIndex] = BIT_FALSE;
@@ -857,7 +857,7 @@
       return false;
 
     if (Insn[StartBit + i] == BIT_TRUE)
-      Field = Field | (1 << i);
+      Field = Field | (1ULL << i);
   }
 
   return true;