[llvm-commits] [llvm] r100651 - /llvm/trunk/lib/Target/ARM/ARMScheduleV7.td
Anton Korobeynikov
asl at math.spbu.ru
Wed Apr 7 11:20:07 PDT 2010
Author: asl
Date: Wed Apr 7 13:20:07 2010
New Revision: 100651
URL: http://llvm.org/viewvc/llvm-project?rev=100651&view=rev
Log:
Some easy NEON scheduling goodness for A9
Modified:
llvm/trunk/lib/Target/ARM/ARMScheduleV7.td
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV7.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV7.td?rev=100651&r1=100650&r2=100651&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleV7.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleV7.td Wed Apr 7 13:20:07 2010
@@ -780,7 +780,59 @@
InstrItinData<IIC_fpMOVDI, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
InstrStage2<2, [FU_DRegsN], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
- InstrStage<1, [FU_NPipe]>], [1, 1, 1]>
+ InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
+ // NEON
+ // Issue through integer pipeline, and execute in NEON unit.
+
+ //
+ // Double-register Integer Binary
+ InstrItinData<IIC_VBINiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
+ // Extra 3 latency cycle since wbck is 6 cycles
+ InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
+ //
+ // Quad-register Integer Binary
+ InstrItinData<IIC_VBINiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
+ // Extra 3 latency cycle since wbck is 6 cycles
+ InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
+ //
+ // Double-register Integer Subtract
+ InstrItinData<IIC_VSUBiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
+ // Extra 3 latency cycle since wbck is 6 cycles
+ InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
+ //
+ // Quad-register Integer Subtract
+ InstrItinData<IIC_VSUBiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
+ // Extra 3 latency cycle since wbck is 6 cycles
+ InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
+ //
+ // Double-register Integer Shift
+ InstrItinData<IIC_VSHLiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
+ // Extra 3 latency cycle since wbck is 6 cycles
+ InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
+ //
+ // Double-register Integer Binary (4 cycle)
+ InstrItinData<IIC_VBINi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>,
+ // Extra 3 latency cycle since wbck is 6 cycles
+ InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
+ //
+ // Quad-register Integer Binary (4 cycle)
+ InstrItinData<IIC_VBINi4Q, [InstrStage2<1, [FU_DRegsN], 0, Required>,
+ // Extra 3 latency cycle since wbck is 6 cycles
+ InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 2, 2]>
]>;
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