[llvm-commits] [llvm] r99752 - /llvm/trunk/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll

[Chris Lattner]

Author: lattner
Date: Sun Mar 28 02:58:37 2010
New Revision: 99752

URL: http://llvm.org/viewvc/llvm-project?rev=99752&view=rev
Log:
add some nounwinds

Modified:
    llvm/trunk/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll

Modified: llvm/trunk/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll?rev=99752&r1=99751&r2=99752&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll Sun Mar 28 02:58:37 2010
@@ -9,66 +9,66 @@
 ; RUN: llc < %s -march=ppc32 | \
 ; RUN:   grep nand | count 1
 
-define i32 @EQV1(i32 %X, i32 %Y) {
+define i32 @EQV1(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, %Y		; <i32> [#uses=1]
 	%B = xor i32 %A, -1		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @EQV2(i32 %X, i32 %Y) {
+define i32 @EQV2(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = xor i32 %A, %Y		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @EQV3(i32 %X, i32 %Y) {
+define i32 @EQV3(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = xor i32 %Y, %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ANDC1(i32 %X, i32 %Y) {
+define i32 @ANDC1(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %Y, -1		; <i32> [#uses=1]
 	%B = and i32 %X, %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ANDC2(i32 %X, i32 %Y) {
+define i32 @ANDC2(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = and i32 %A, %Y		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ORC1(i32 %X, i32 %Y) {
+define i32 @ORC1(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %Y, -1		; <i32> [#uses=1]
 	%B = or i32 %X, %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ORC2(i32 %X, i32 %Y) {
+define i32 @ORC2(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = or i32 %A, %Y		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @NOR1(i32 %X) {
+define i32 @NOR1(i32 %X) nounwind {
 	%Y = xor i32 %X, -1		; <i32> [#uses=1]
 	ret i32 %Y
 }
 
-define i32 @NOR2(i32 %X, i32 %Y) {
+define i32 @NOR2(i32 %X, i32 %Y) nounwind {
 	%Z = or i32 %X, %Y		; <i32> [#uses=1]
 	%R = xor i32 %Z, -1		; <i32> [#uses=1]
 	ret i32 %R
 }
 
-define i32 @NAND1(i32 %X, i32 %Y) {
+define i32 @NAND1(i32 %X, i32 %Y) nounwind {
 	%Z = and i32 %X, %Y		; <i32> [#uses=1]
 	%W = xor i32 %Z, -1		; <i32> [#uses=1]
 	ret i32 %W
 }
 
-define void @VNOR(<4 x float>* %P, <4 x float>* %Q) {
+define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind {
 	%tmp = load <4 x float>* %P		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp2 = load <4 x float>* %Q		; <<4 x float>> [#uses=1]
@@ -80,7 +80,7 @@
 	ret void
 }
 
-define void @VANDC(<4 x float>* %P, <4 x float>* %Q) {
+define void @VANDC(<4 x float>* %P, <4 x float>* %Q) nounwind {
 	%tmp = load <4 x float>* %P		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp2 = load <4 x float>* %Q		; <<4 x float>> [#uses=1]