[llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td

[Johnny Chen]

I will rename NVdVmImmFrm to the more proper N2RegFrm.
N2V2 is still necessary, though, because of N2VS, N2VD, N2VQ, which are for vcvt instructions.

On Mar 23, 2010, at 2:45 PM, Bob Wilson wrote:

> 
> On Mar 23, 2010, at 2:25 PM, Johnny Chen wrote:
> 
>> Author: johnny
>> Date: Tue Mar 23 16:25:38 2010
>> New Revision: 99326
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
>> Log:
>> Add New NEON Format NVdVmVCVTFrm.
>> Converted some of the NEON vcvt instructions to this format.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>   llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
>> @@ -62,6 +62,7 @@
>> def NLdStFrm                : Format<31>;
>> def NVdImmFrm               : Format<32>;
>> def NVdVmImmFrm             : Format<33>;
>> +def NVdVmVCVTFrm            : Format<34>;
> 
> How about "NVCVTFrm"?
> 
> 
>> 
>> // Misc flags.
>> 
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
>> @@ -853,25 +853,40 @@
>> // Instruction Classes
>> //===----------------------------------------------------------------------===//
>> 
>> +// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
>> +class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
>> +          bits<5> op11_7, bit op6, bit op4,
>> +          dag oops, dag iops, Format f, InstrItinClass itin,
>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>> +  let Inst{24-23} = op24_23;
>> +  let Inst{21-20} = op21_20;
>> +  let Inst{19-18} = op19_18;
>> +  let Inst{17-16} = op17_16;
>> +  let Inst{11-7} = op11_7;
>> +  let Inst{6} = op6;
>> +  let Inst{4} = op4;
>> +}
>> +
> 
> This should not be necessary.  You should not have added the NVdVmImmFrm for N2V to begin with (per my earlier comments).  Please remove this class.
> 
> 
>> // Basic 2-register operations: single-, double- and quad-register.
>> class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>           bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>           string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>> -        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
>> -        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>> +         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
>> +         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>> class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>           bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>           string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>> -        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
>> -        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>> +         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
>> +         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>> class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>           bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>           string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>> -        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
>> -        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>> +         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
>> +         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>> 
>> // Basic 2-register intrinsics, both double- and quad-register.
>> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>> 
>> 
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