[llvm-commits] [llvm] r99043 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

[Bob Wilson]

Author: bwilson
Date: Sat Mar 20 01:05:13 2010
New Revision: 99043

URL: http://llvm.org/viewvc/llvm-project?rev=99043&view=rev
Log:
Fix a very bad typo.  Since the register number was off by one, the ARM
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=99043&r1=99042&r2=99043&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sat Mar 20 01:05:13 2010
@@ -80,7 +80,7 @@
   case D23: return 23;
   case D24: return 24;
   case D25: return 25;
-  case D26: return 27;
+  case D26: return 26;
   case D27: return 27;
   case D28: return 28;
   case D29: return 29;