[llvm-commits] [llvm] r99000 - in /llvm/trunk/lib/Target/X86: X86Instr64bit.td X86InstrInfo.td
Chris Lattner
sabre at nondot.org
Fri Mar 19 14:43:36 PDT 2010
Author: lattner
Date: Fri Mar 19 16:43:36 2010
New Revision: 99000
URL: http://llvm.org/viewvc/llvm-project?rev=99000&view=rev
Log:
remove the patterns that I commented out in r98930, Dan verified
that they are dead.
Modified:
llvm/trunk/lib/Target/X86/X86Instr64bit.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=99000&r1=98999&r2=99000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Fri Mar 19 16:43:36 2010
@@ -2232,22 +2232,6 @@
def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
(implicit EFLAGS)),
(ADD64rm GR64:$src1, addr:$src2)>;
-/*
-// Memory-Register Addition with EFLAGS result
-def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD64mr addr:$dst, GR64:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
- i64immSExt32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
-*/
// Register-Register Subtraction with EFLAGS result
def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
@@ -2267,26 +2251,6 @@
(implicit EFLAGS)),
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
-/*
-// Memory-Register Subtraction with EFLAGS result
-def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB64mr addr:$dst, GR64:$src2)>;
-
-// Memory-Integer Subtraction with EFLAGS result
-def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
- i64immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
-def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
- i64immSExt32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
-*/
-
// Register-Register Signed Integer Multiplication with EFLAGS result
def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
(implicit EFLAGS)),
@@ -2316,45 +2280,18 @@
// INC and DEC with EFLAGS result. Note that these do not set CF.
def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
(INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
-/*
-def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/
def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
(DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
-/*
-def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/
def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
(INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
-/*
-def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;*/
def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
(DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
-/*
-def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
-*/
def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
(INC64r GR64:$src)>;
-/*
-def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (INC64m addr:$dst)>;
- */
def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
(DEC64r GR64:$src)>;
-/*
-def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (DEC64m addr:$dst)>;
- */
// Register-Register Logical Or with EFLAGS result
def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
@@ -2374,22 +2311,6 @@
(implicit EFLAGS)),
(OR64rm GR64:$src1, addr:$src2)>;
-// Memory-Register Logical Or with EFLAGS result
-/*
-def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR64mr addr:$dst, GR64:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
-*/
-
// Register-Register Logical XOr with EFLAGS result
def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
(implicit EFLAGS)),
@@ -2408,23 +2329,6 @@
(implicit EFLAGS)),
(XOR64rm GR64:$src1, addr:$src2)>;
-// Memory-Register Logical XOr with EFLAGS result
-/*
-def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR64mr addr:$dst, GR64:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
- i64immSExt32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
-*/
-
// Register-Register Logical And with EFLAGS result
def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
(implicit EFLAGS)),
@@ -2443,23 +2347,6 @@
(implicit EFLAGS)),
(AND64rm GR64:$src1, addr:$src2)>;
-// Memory-Register Logical And with EFLAGS result
-/*
-def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND64mr addr:$dst, GR64:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
- i64immSExt32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
-*/
-
//===----------------------------------------------------------------------===//
// X86-64 SSE Instructions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99000&r1=98999&r2=99000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Mar 19 16:43:36 2010
@@ -4785,44 +4785,6 @@
(implicit EFLAGS)),
(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
-/*
-// Memory-Register Addition with EFLAGS result
-def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD8mr addr:$dst, GR8:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD16mr addr:$dst, GR16:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD32mr addr:$dst, GR32:$src2)>;
-
-// Memory-Integer Addition with EFLAGS result
-def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD8mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD16mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD32mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
-def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
-*/
-
// Register-Register Subtraction with EFLAGS result
def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
(implicit EFLAGS)),
@@ -4862,44 +4824,6 @@
(implicit EFLAGS)),
(SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
-/*
-// Memory-Register Subtraction with EFLAGS result
-def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB8mr addr:$dst, GR8:$src2)>;
-def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB16mr addr:$dst, GR16:$src2)>;
-def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB32mr addr:$dst, GR32:$src2)>;
-
-// Memory-Integer Subtraction with EFLAGS result
-def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB8mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB16mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB32mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
-def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
-*/
-
// Register-Register Signed Integer Multiply with EFLAGS result
def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
(implicit EFLAGS)),
@@ -4958,40 +4882,18 @@
// INC and DEC with EFLAGS result. Note that these do not set CF.
def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
(INC8r GR8:$src)>;
- /*
-def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (INC8m addr:$dst)>;
- */
def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
(DEC8r GR8:$src)>;
-/*def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (DEC8m addr:$dst)>;*/
def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
(INC16r GR16:$src)>, Requires<[In32BitMode]>;
-/*
-def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (INC16m addr:$dst)>, Requires<[In32BitMode]>;*/
def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
(DEC16r GR16:$src)>, Requires<[In32BitMode]>;
-/*
-def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (DEC16m addr:$dst)>, Requires<[In32BitMode]>;*/
def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
(INC32r GR32:$src)>, Requires<[In32BitMode]>;
-/*def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (INC32m addr:$dst)>, Requires<[In32BitMode]>;*/
def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
(DEC32r GR32:$src)>, Requires<[In32BitMode]>;
-/*def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
- (implicit EFLAGS)),
- (DEC32m addr:$dst)>, Requires<[In32BitMode]>;*/
// Register-Register Or with EFLAGS result
def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
@@ -5031,43 +4933,6 @@
def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
(implicit EFLAGS)),
(OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
-/*
-// Memory-Register Or with EFLAGS result
-def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR8mr addr:$dst, GR8:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR16mr addr:$dst, GR16:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR32mr addr:$dst, GR32:$src2)>;
-
-// Memory-Integer Or with EFLAGS result
-def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR8mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR16mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR32mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
-def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
- */
// Register-Register XOr with EFLAGS result
def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
@@ -5108,44 +4973,6 @@
(implicit EFLAGS)),
(XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
-/*
-// Memory-Register XOr with EFLAGS result
-def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR8mr addr:$dst, GR8:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR16mr addr:$dst, GR16:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR32mr addr:$dst, GR32:$src2)>;
-
-// Memory-Integer XOr with EFLAGS result
-def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR8mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR16mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR32mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
-def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
-*/
-
// Register-Register And with EFLAGS result
def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
(implicit EFLAGS)),
@@ -5185,44 +5012,6 @@
(implicit EFLAGS)),
(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
-/*
-// Memory-Register And with EFLAGS result
-def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND8mr addr:$dst, GR8:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND16mr addr:$dst, GR16:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND32mr addr:$dst, GR32:$src2)>;
-
-// Memory-Integer And with EFLAGS result
-def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND8mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND16mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND32mi addr:$dst, imm:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
-def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
- addr:$dst),
- (implicit EFLAGS)),
- (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
-*/
-
// -disable-16bit support.
def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
(MOV16mi addr:$dst, imm:$src)>;
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