[llvm-commits] [llvm] r98972 - in /llvm/trunk: lib/Target/X86/X86Instr64bit.td test/MC/AsmParser/X86/x86_64-new-encoder.s

[Chris Lattner]

On Mar 19, 2010, at 11:07 AM, Daniel Dunbar wrote:

> Author: ddunbar
> Date: Fri Mar 19 13:07:48 2010
> New Revision: 98972
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=98972&view=rev
> Log:
> MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.

maybe these should be marked "disassembler only"?

-Chris

> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86Instr64bit.td
>    llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s
> 
> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=98972&r1=98971&r2=98972&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Fri Mar 19 13:07:48 2010
> @@ -511,6 +511,14 @@
>                     [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
>                      (implicit EFLAGS)]>;
> 
> +// These are alternate spellings for use by the disassembler, we mark them as
> +// code gen only to ensure they aren't matched by the assembler.
> +let isCodeGenOnly = 1 in {
> +  def ADD64rr_alt  : RI<0x03, MRMSrcReg, (outs GR64:$dst), 
> +                       (ins GR64:$src1, GR64:$src2),
> +                       "add{l}\t{$src2, $dst|$dst, $src2}", []>;
> +}
> +
> // Register-Integer Addition
> def ADD64ri8  : RIi8<0x83, MRM0r, (outs GR64:$dst), 
>                      (ins GR64:$src1, i64i8imm:$src2),
> @@ -531,12 +539,6 @@
>                      [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
>                       (implicit EFLAGS)]>;
> 
> -// Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
> -//   differently encoded.
> -def ADD64mrmrr  : RI<0x03, MRMSrcReg, (outs GR64:$dst), 
> -                     (ins GR64:$src1, GR64:$src2),
> -                     "add{l}\t{$src2, $dst|$dst, $src2}", []>;
> -
> } // isTwoAddress
> 
> // Memory-Register Addition
> @@ -1249,8 +1251,14 @@
> def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
>                  "cmp{q}\t{$src2, $src1|$src1, $src2}",
>                  [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
> -def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
> -                    "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
> +
> +// These are alternate spellings for use by the disassembler, we mark them as
> +// code gen only to ensure they aren't matched by the assembler.
> +let isCodeGenOnly = 1 in {
> +  def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
> +                      "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
> +}
> +
> def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
>                  "cmp{q}\t{$src2, $src1|$src1, $src2}",
>                  [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
> 
> Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=98972&r1=98971&r2=98972&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original)
> +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Fri Mar 19 13:07:48 2010
> @@ -48,3 +48,7 @@
> // CHECK: testq	%rax, %rbx
> // CHECK:  encoding: [0x48,0x85,0xd8]
> testq %rax, %rbx
> +
> +// CHECK: cmpq	%rbx, %r14
> +// CHECK:   encoding: [0x49,0x39,0xde]
> +        cmpq %rbx, %r14
> 
> 
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