[llvm-commits] [llvm] r98900 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp DAGISelMatcherGen.cpp

[Chris Lattner]

Author: lattner
Date: Thu Mar 18 18:57:40 2010
New Revision: 98900

URL: http://llvm.org/viewvc/llvm-project?rev=98900&view=rev
Log:
expand tblgen's  support for instructions with implicit defs.


Modified:
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
    llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=98900&r1=98899&r2=98900&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Thu Mar 18 18:57:40 2010
@@ -1163,12 +1163,14 @@
     } else if (!InstInfo.ImplicitDefs.empty()) {
       // If the instruction has implicit defs, the first one defines the result
       // type.
-      assert(InstInfo.ImplicitDefs[0]->isSubClassOf("Register"));
       Record *FirstImplicitDef = InstInfo.ImplicitDefs[0];
+      assert(FirstImplicitDef->isSubClassOf("Register"));
       const std::vector<MVT::SimpleValueType> &RegVTs = 
         CDP.getTargetInfo().getRegisterVTs(FirstImplicitDef);
-      if (!RegVTs.empty())
+      if (RegVTs.size() == 1)
         ResultType = EEVT::TypeSet(RegVTs);
+      else
+        ResultType = EEVT::TypeSet(MVT::isVoid, TP);
     } else {
       // Otherwise, the instruction produces no value result.
       // FIXME: Model "no result" different than "one result that is void"

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp?rev=98900&r1=98899&r2=98900&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp Thu Mar 18 18:57:40 2010
@@ -698,7 +698,7 @@
     // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
     for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
       AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
-                                                  PhysRegInputs[i].first));
+                                          PhysRegInputs[i].first));
     // Even if the node has no other flag inputs, the resultant node must be
     // flagged to the CopyFromReg nodes we just generated.
     TreeHasInFlag = true;
@@ -708,12 +708,11 @@
   
   // Determine the result types.
   SmallVector<MVT::SimpleValueType, 4> ResultVTs;
-  if (NumResults != 0 && N->getType() != MVT::isVoid) {
+  if (N->getType() != MVT::isVoid) {
     // FIXME2: If the node has multiple results, we should add them.  For now,
     // preserve existing behavior?!
     ResultVTs.push_back(N->getType());
   }
-
   
   // If this is the root instruction of a pattern that has physical registers in
   // its result pattern, add output VTs for them.  For example, X86 has:
@@ -721,9 +720,18 @@
   // This also handles implicit results like:
   //   (implicit EFLAGS)
   if (isRoot && Pattern.getDstRegs().size() != 0) {
-    for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
-      if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
-        ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
+    // If the root came from an implicit def in the instruction handling stuff,
+    // don't re-add it.
+    Record *HandledReg = 0;
+    if (NumResults == 0 && N->getType() != MVT::isVoid &&
+        !II.ImplicitDefs.empty())
+      HandledReg = II.ImplicitDefs[0];
+    
+    for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
+      Record *Reg = Pattern.getDstRegs()[i];
+      if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
+      ResultVTs.push_back(getRegisterValueType(Reg, CGT));
+    }
   }
 
   // FIXME2: Instead of using the isVariadic flag on the instruction, we should