[llvm-commits] [llvm] r98839 - in /llvm/trunk: lib/Target/X86/X86FixupKinds.h lib/Target/X86/X86MCCodeEmitter.cpp test/MC/AsmParser/X86/x86_64-new-encoder.s
Chris Lattner
sabre at nondot.org
Thu Mar 18 11:10:56 PDT 2010
Author: lattner
Date: Thu Mar 18 13:10:56 2010
New Revision: 98839
URL: http://llvm.org/viewvc/llvm-project?rev=98839&view=rev
Log:
add a special relocation type for movq loads for object
files that produce special relocation types where the
linker changes movq's into lea's.
Modified:
llvm/trunk/lib/Target/X86/X86FixupKinds.h
llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s
Modified: llvm/trunk/lib/Target/X86/X86FixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupKinds.h?rev=98839&r1=98838&r2=98839&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FixupKinds.h (original)
+++ llvm/trunk/lib/Target/X86/X86FixupKinds.h Thu Mar 18 13:10:56 2010
@@ -17,7 +17,8 @@
enum Fixups {
reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch.
reloc_pcrel_1byte, // 8-bit pcrel, e.g. branch_1
- reloc_riprel_4byte // 32-bit rip-relative
+ reloc_riprel_4byte, // 32-bit rip-relative
+ reloc_riprel_4byte_movq_load // 32-bit rip-relative in movq
};
}
}
Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=98839&r1=98838&r2=98839&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Thu Mar 18 13:10:56 2010
@@ -38,14 +38,15 @@
~X86MCCodeEmitter() {}
unsigned getNumFixupKinds() const {
- return 3;
+ return 4;
}
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[] = {
{ "reloc_pcrel_4byte", 0, 4 * 8 },
{ "reloc_pcrel_1byte", 0, 1 * 8 },
- { "reloc_riprel_4byte", 0, 4 * 8 }
+ { "reloc_riprel_4byte", 0, 4 * 8 },
+ { "reloc_riprel_4byte_movq_load", 0, 4 * 8 }
};
if (Kind < FirstTargetFixupKind)
@@ -197,6 +198,14 @@
"Invalid rip-relative address");
EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
+ unsigned FixupKind = X86::reloc_riprel_4byte;
+
+ // movq loads are handled with a special relocation form which allows the
+ // linker to eliminate some loads for GOT references which end up in the
+ // same linkage unit.
+ if (MI.getOpcode() == X86::MOV64rm_TC)
+ FixupKind = X86::reloc_riprel_4byte_movq_load;
+
// rip-relative addressing is actually relative to the *next* instruction.
// Since an immediate can follow the mod/rm byte for an instruction, this
// means that we need to bias the immediate field of the instruction with
@@ -204,7 +213,7 @@
// expression to emit.
int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
- EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_riprel_4byte),
+ EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
CurByte, OS, Fixups, -ImmSize);
return;
}
Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=98839&r1=98838&r2=98839&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Thu Mar 18 13:10:56 2010
@@ -25,5 +25,13 @@
// CHECK: encoding: [0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
// CHECK: fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte
-// CHECK: addq $-424, %rax # encoding: [0x48,0x05,0x58,0xfe,0xff,0xff]
+// CHECK: addq $-424, %rax
+// CHECK: encoding: [0x48,0x05,0x58,0xfe,0xff,0xff]
addq $-424, %rax
+
+
+// CHECK: movq _foo at GOTPCREL(%rip), %rax
+// CHECK: encoding: [0x48,0x8b,0x05,A,A,A,A]
+// CHECK: fixup A - offset: 3, value: _foo at GOTPCREL, kind: reloc_riprel_4byte_movq_load
+movq _foo at GOTPCREL(%rip), %rax
+
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