[llvm-commits] [www-pubs] r98807 - in /www-pubs/trunk: 2010-02-FPGA-BitLevel.html 2010-02-FPGA-BitLevel.pdf pubs.js

Wed Mar 17 23:43:15 PDT 2010

Author: resistor
Date: Thu Mar 18 01:43:15 2010
New Revision: 98807

URL: http://llvm.org/viewvc/llvm-project?rev=98807&view=rev
Log:
Add a paper from FPGA'10.

Added:
    www-pubs/trunk/2010-02-FPGA-BitLevel.html
    www-pubs/trunk/2010-02-FPGA-BitLevel.pdf
Modified:
    www-pubs/trunk/pubs.js

Added: www-pubs/trunk/2010-02-FPGA-BitLevel.html
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-02-FPGA-BitLevel.html?rev=98807&view=auto
==============================================================================

--- www-pubs/trunk/2010-02-FPGA-BitLevel.html (added)
+++ www-pubs/trunk/2010-02-FPGA-BitLevel.html Thu Mar 18 01:43:15 2010
@@ -0,0 +1,48 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <link rel="stylesheet" href="../llvm.css" type="text/css" media="screen">
+  <title>Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration</title>
+</head>
+<body>
+
+<div class="pub_title">
+  Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration
+</div>
+<div class="pub_author">
+ Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong
+</div>
+
+<h2>Abstract:</h2>
+<blockquote>
+<p>Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level programming languages, such as C/C++, the description of bitwise access and computation is not as direct as hardware description languages, and high-level synthesis of algorithmic descriptions may generate suboptimal implementations for bitwise computation-intensive applications. In this paper we introduce a bit-level transformation and optimization approach to assisting high-level synthesis of algorithmic descriptions. We introduce a bit-flow graph to capture bit-value information. Analysis and optimizing transformations can be performed on this representation, and the optimized results are transformed back to the standard data-flow graphs extended with a few instructions representing bitwise access. This allows high-level synthesis tools to automatically generate circuits with higher quality.
  Experiments show that our algorithm can reduce slice usage by 29.8% on average for a set of real-life benchmarks on Xilinx Virtex-4 FPGAs. In the meantime, the clock period is reduced by 13.6% on average, with an 11.4% latency reduction.</p>
+</blockquote>
+
+<h2>Published:</h2>
+<blockquote>
+  "Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration"
+  <br>
+  Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong
+  <br>
+<i>
+Proc. of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays
+</i>, Monterey, CA, February 2010.
+</blockquote>
+<h2>Download:</h2>
+<h3>Paper:</h3>
+<ul>
+  <li><a href="2010-02-FPGA-BitLevel.pdf">
+  Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration
+  </a> (PDF)</li>
+</ul>
+
+<!-- *********************************************************************** -->
+<hr>
+  <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
+  src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"></a>
+  <a href="http://validator.w3.org/check/referer"><img
+  src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
+
+</body>
+</html>

Added: www-pubs/trunk/2010-02-FPGA-BitLevel.pdf
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-02-FPGA-BitLevel.pdf?rev=98807&view=auto
==============================================================================
Binary files www-pubs/trunk/2010-02-FPGA-BitLevel.pdf (added) and www-pubs/trunk/2010-02-FPGA-BitLevel.pdf Thu Mar 18 01:43:15 2010 differ

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=98807&r1=98806&r2=98807&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Thu Mar 18 01:43:15 2010
@@ -43,14 +43,20 @@
    location: "Pittsburgh, PA",
    month: 3,
    year: 2010},
-
-  {url: "2010-01-Wennborg-Thesis.html",
-   title: "Emulator Speed-up Using JIT and LLVM",
-   published: "Master's Thesis, Lund University",
-   location: "Lund, Sweden",
-   author: "Hans Wennborg",
-   month: 1,
+  {url: "2010-02-FPGA-BitLevel.html",
+   title: "Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration",
+   published: "Proc. of the 18th Annual ACM/SIGDA International Symposium on Field programmable Gate Arrays (FPGA'10)",
+   author: "Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong",
+   location: "Monterey, CA",
+   month: 2,
    year: 2010},
+  {url: "2010-01-Wennborg-Thesis.html",
+    title: "Emulator Speed-up Using JIT and LLVM",
+    published: "Master's Thesis, Lund University",
+    location: "Lund, Sweden",
+    author: "Hans Wennborg",
+    month: 1,
+    year: 2010},
 
   {url: "2009-10-LCPC-DataRestructuring.html",
    title: "Automatic Restructuring of Linked Data Structures",



