[llvm-commits] [llvm] r98775 - /llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

[Johnny Chen]

Author: johnny
Date: Wed Mar 17 18:14:23 2010
New Revision: 98775

URL: http://llvm.org/viewvc/llvm-project?rev=98775&view=rev
Log:
Fixed a bug in the IT mask printing where T means the cond bit in the mask
matches that of Firstcond[0] and E means otherwise.  The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing.  The disassembler also depends
on this arrangement.  This is similar to what's described in A2.5.2 ITSTATE.

Ran:

utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2

successfully.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=98775&r1=98774&r2=98775&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Wed Mar 17 18:14:23 2010
@@ -78,14 +78,16 @@
       DebugLoc ndl = NMI->getDebugLoc();
       unsigned NPredReg = 0;
       ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
-      if (NCC == OCC) {
-        Mask |= (1 << Pos);
-      } else if (NCC != CC)
+      if (NCC == CC || NCC == OCC)
+        Mask |= (NCC & 1) << Pos;
+      else
         break;
       --Pos;
       ++MBBI;
     }
     Mask |= (1 << Pos);
+    // Tag along (firstcond[0] << 4) with the mask.
+    Mask |= (CC & 1) << 4;
     MIB.addImm(Mask);
     Modified = true;
     ++NumITs;