[llvm-commits] [llvm] r98637 - in /llvm/trunk: ./ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/ARM/Disassembler/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ utils/TableGen/

[Anton Korobeynikov]

Hi, Johny

> Initial ARM/Thumb disassembler check-in.  It consists of a tablgen backend
> (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
> and the disassembler core which invokes the decoder function and builds up the
> MCInst based on the decoded Opcode.
Quick q: here RISC means "completely fixed length"? Or, say, the
instructions might be 16/32/24 bits length (contain 1/2 optional
address fields)?

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University