[llvm-commits] [llvm] r98098 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/AsmParser/X86/x86_32-new-encoder.s

[Daniel Dunbar]

Author: ddunbar
Date: Tue Mar  9 16:50:46 2010
New Revision: 98098

URL: http://llvm.org/viewvc/llvm-project?rev=98098&view=rev
Log:
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=98098&r1=98097&r2=98098&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar  9 16:50:46 2010
@@ -2647,6 +2647,17 @@
 } // end isConvertibleToThreeAddress
 } // end isCommutable
 
+// These are alternate spellings for use by the disassembler, we mark them as
+// code gen only to ensure they aren't matched by the assembler.
+let isCodeGenOnly = 1 in {
+  def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                   "add{b}\t{$src2, $dst|$dst, $src2}", []>;
+  def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
+                    "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
+  def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
+                    "add{l}\t{$src2, $dst|$dst, $src2}", []>;
+}
+
 // Register-Memory Addition
 def ADD8rm   : I<0x02, MRMSrcMem, (outs GR8 :$dst),
                                   (ins GR8 :$src1, i8mem :$src2),
@@ -2664,15 +2675,6 @@
                  [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
                   (implicit EFLAGS)]>;
                   
-// Register-Register Addition - Equivalent to the normal rr forms (ADD8rr, 
-//   ADD16rr, and ADD32rr), but differently encoded.
-def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
-                 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
-def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
-                  "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
-def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
-                  "add{l}\t{$src2, $dst|$dst, $src2}", []>;
-
 // Register-Integer Addition
 def ADD8ri    : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
                     "add{b}\t{$src2, $dst|$dst, $src2}",

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=98098&r1=98097&r2=98098&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Tue Mar  9 16:50:46 2010
@@ -44,3 +44,6 @@
 
 // CHECK: cmpl	%eax, %ebx              # encoding: [0x39,0xc3]
         cmpl %eax, %ebx
+
+// CHECK: addw	%ax, %ax                # encoding: [0x66,0x01,0xc0]
+        addw %ax, %ax