[llvm-commits] [llvm] r97006 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/2010-02-23-DIV8rDefinesAX.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Tue Feb 23 18:39:35 2010
New Revision: 97006

URL: http://llvm.org/viewvc/llvm-project?rev=97006&view=rev
Log:
DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses it
instead of %AL/%AH.

Added:
    llvm/trunk/test/CodeGen/X86/2010-02-23-DIV8rDefinesAX.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=97006&r1=97005&r2=97006&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Feb 23 18:39:35 2010
@@ -1156,7 +1156,7 @@
 } // neverHasSideEffects
 
 // unsigned division/remainder
-let Defs = [AL,AH,EFLAGS], Uses = [AX] in
+let Defs = [AX,EFLAGS], Uses = [AX] in
 def DIV8r  : I<0xF6, MRM6r, (outs),  (ins GR8:$src),    // AX/r8 = AL,AH
                "div{b}\t$src", []>;
 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in

Added: llvm/trunk/test/CodeGen/X86/2010-02-23-DIV8rDefinesAX.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-02-23-DIV8rDefinesAX.ll?rev=97006&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-02-23-DIV8rDefinesAX.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2010-02-23-DIV8rDefinesAX.ll Tue Feb 23 18:39:35 2010
@@ -0,0 +1,20 @@
+; RUN: llc < %s
+; PR6374
+;
+; This test produces a DIV8r instruction and uses %AX instead of %AH and %AL.
+; The DIV8r must have the right imp-defs for that to work.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.0.0"
+
+%struct._i386_state = type { %union.anon }
+%union.anon = type { [0 x i8] }
+
+define void @i386_aam(%struct._i386_state* nocapture %cpustate) nounwind ssp {
+entry:
+  %call = tail call fastcc signext i8 @FETCH()    ; <i8> [#uses=1]
+  %rem = urem i8 0, %call                         ; <i8> [#uses=1]
+  store i8 %rem, i8* undef
+  ret void
+}
+
+declare fastcc signext i8 @FETCH() nounwind readnone ssp