[llvm-commits] [llvm] r96654 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Chris Lattner]

On Feb 19, 2010, at 3:36 PM, Johnny Chen wrote:

> OK.  I've modified ARMInstPrinter.cpp to handle the printing of ARM::MOVs:

Great, thanks!!

-Chris

> 
> void ARMInstPrinter::printInst(const MCInst *MI) {
>  // Check for MOVs and print canonical forms, instead.
>  if (MI->getOpcode() == ARM::MOVs) {
>    const MCOperand &Dst = MI->getOperand(0);
>    const MCOperand &MO1 = MI->getOperand(1);
>    const MCOperand &MO2 = MI->getOperand(2);
>    const MCOperand &MO3 = MI->getOperand(3);
> 
>    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
>    printSBitModifierOperand(MI, 6);
>    printPredicateOperand(MI, 4);
> 
>    O << '\t' << getRegisterName(Dst.getReg())
>      << ", " << getRegisterName(MO1.getReg());
> 
>    if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
>      return;
> 
>    O << ", ";
> 
>    if (MO2.getReg()) {
>      O << getRegisterName(MO2.getReg());
>      assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
>    } else {
>      O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
>    }
>    return;
>  }
> 
>  printInstruction(MI);
> }
> 
> I will modify ARMInstrInfo.td to remove the entries in a minute.
> 
> Thanks.
> 
> On Feb 19, 2010, at 2:00 PM, Chris Lattner wrote:
> 
>> 
>> On Feb 19, 2010, at 11:33 AM, Johnny Chen wrote:
>> 
>>> Hi Chris,
>>> 
>>> These added encodings are are more specific than:
>>> 
>>> def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
>>>              DPSoRegFrm, IIC_iMOVsr,
>>>              "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
>>> let Inst{25} = 0;
>>> }
>>> 
>>> Relying on the decoder to decode a MOVs super-instruction would mean that
>>> it prints out:
>>> 
>>> 	mov		r0, r0, asr #1
>>> 
>>> which, according to A8.6.98, is a pseudo-instruction and is not the canonical form we want
>>> for disassembly (A8-199).  And an added bonus is that MOVs cannot handle RRX (A8-282).
>> 
>> I'm not sure I understand here.  You added a redundant encoding for the same bits, yes?
>> 
>> If this is the case, it is better to handle this with code like PPCAsmPrinter::EmitInstruction, where the decoder produces the general 'mov' form of the MCInst, but then the MCInst -> text printer handles the special pseudo op.
>> 
>> -Chris
>> 
>