[llvm-commits] [llvm] r96654 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Chris Lattner]

On Feb 19, 2010, at 11:33 AM, Johnny Chen wrote:

> Hi Chris,
> 
> These added encodings are are more specific than:
> 
> def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
>                DPSoRegFrm, IIC_iMOVsr,
>                "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
>  let Inst{25} = 0;
> }
> 
> Relying on the decoder to decode a MOVs super-instruction would mean that
> it prints out:
> 
> 	mov		r0, r0, asr #1
> 
> which, according to A8.6.98, is a pseudo-instruction and is not the canonical form we want
> for disassembly (A8-199).  And an added bonus is that MOVs cannot handle RRX (A8-282).

I'm not sure I understand here.  You added a redundant encoding for the same bits, yes?

If this is the case, it is better to handle this with code like PPCAsmPrinter::EmitInstruction, where the decoder produces the general 'mov' form of the MCInst, but then the MCInst -> text printer handles the special pseudo op.

-Chris