[llvm-commits] [llvm] r96040 - in /llvm/trunk: lib/Target/X86/X86MCCodeEmitter.cpp test/MC/AsmParser/X86/x86_64-new-encoder.s
Chris Lattner
sabre at nondot.org
Fri Feb 12 15:24:10 PST 2010
Author: lattner
Date: Fri Feb 12 17:24:09 2010
New Revision: 96040
URL: http://llvm.org/viewvc/llvm-project?rev=96040&view=rev
Log:
implement the rest of correct x86-64 encoder support for
rip-relative addresses, and add a testcase.
Added:
llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s
Modified:
llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=96040&r1=96039&r2=96040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Fri Feb 12 17:24:09 2010
@@ -15,6 +15,7 @@
#include "X86.h"
#include "X86InstrInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -36,10 +37,11 @@
void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
const TargetMachine &TM;
const TargetInstrInfo &TII;
+ MCContext &Ctx;
bool Is64BitMode;
public:
- X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
- : TM(tm), TII(*TM.getInstrInfo()) {
+ X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
+ : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
Is64BitMode = is64Bit;
}
@@ -122,13 +124,13 @@
MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
TargetMachine &TM,
MCContext &Ctx) {
- return new X86MCCodeEmitter(TM, false);
+ return new X86MCCodeEmitter(TM, Ctx, false);
}
MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
TargetMachine &TM,
MCContext &Ctx) {
- return new X86MCCodeEmitter(TM, true);
+ return new X86MCCodeEmitter(TM, Ctx, true);
}
@@ -167,7 +169,9 @@
// If we have an immoffset, add it to the expression.
const MCExpr *Expr = DispOp.getExpr();
- // FIXME: NO CONTEXT.
+ if (ImmOffset)
+ Expr = MCBinaryExpr::CreateAdd(Expr,MCConstantExpr::Create(ImmOffset, Ctx),
+ Ctx);
// Emit a symbolic constant as a fixup and 4 zeros.
Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
Added: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=96040&view=auto
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (added)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Fri Feb 12 17:24:09 2010
@@ -0,0 +1,30 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding --enable-new-x86-encoder %s | FileCheck %s
+
+movl foo(%rip), %eax
+// CHECK: movl foo(%rip), %eax
+// CHECK: encoding: [0x8b,0x05,A,A,A,A]
+// CHECK: fixup A - offset: 2, value: foo, kind: reloc_riprel_4byte
+
+movb $12, foo(%rip)
+// CHECK: movb $12, foo(%rip)
+// CHECK: encoding: [0xc6,0x05,A,A,A,A,B]
+// CHECK: fixup A - offset: 2, value: foo-1, kind: reloc_riprel_4byte
+// CHECK: fixup B - offset: 6, value: 12, kind: FK_Data_1
+
+movw $12, foo(%rip)
+// CHECK: movw $12, foo(%rip)
+// CHECK: encoding: [0x66,0xc7,0x05,A,A,A,A,B,B]
+// CHECK: fixup A - offset: 3, value: foo-2, kind: reloc_riprel_4byte
+// CHECK: fixup B - offset: 7, value: 12, kind: FK_Data_2
+
+movl $12, foo(%rip)
+// CHECK: movl $12, foo(%rip)
+// CHECK: encoding: [0xc7,0x05,A,A,A,A,B,B,B,B]
+// CHECK: fixup A - offset: 2, value: foo-4, kind: reloc_riprel_4byte
+// CHECK: fixup B - offset: 6, value: 12, kind: FK_Data_4
+
+movq $12, foo(%rip)
+// CHECK: movq $12, foo(%rip)
+// CHECK: encoding: [0x48,0xc7,0x05,A,A,A,A,B,B,B,B]
+// CHECK: fixup A - offset: 3, value: foo-4, kind: reloc_riprel_4byte
+// CHECK: fixup B - offset: 7, value: 12, kind: FK_Data_4
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