[llvm-commits] [llvm] r95999 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Chris Lattner]

On Feb 12, 2010, at 11:26 AM, Johnny Chen wrote:

> Yes.  I've been adding test cases while adding instructions to the tables;
> and using a perl script to drive the regression testsuite.

Ok, please wire up llvm-mc so that it can drive the arm diassembler, then you can add tests like the x86 tests in test/MC/Disassembler/simple-tests.txt 

-Chris


> 
> On Feb 12, 2010, at 11:13 AM, Chris Lattner wrote:
> 
>> 
>> On Feb 12, 2010, at 10:55 AM, Johnny Chen wrote:
>> 
>>> Author: johnny
>>> Date: Fri Feb 12 12:55:33 2010
>>> New Revision: 95999
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=95999&view=rev
>>> Log:
>>> Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
>> 
>> Hi Johnny,
>> 
>> Is your disassembler far enough along that it can plug into MCDisassembler framework?  If so, you should be able to write testcases for all these things you're adding, to make sure we don't regress in the future.
>> 
>> -Chris
>> 
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=95999&r1=95998&r2=95999&view=diff
>>> 
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Feb 12 12:55:33 2010
>>> @@ -621,6 +621,21 @@
>>> let Inst{7-4} = 0b0111;
>>> }
>>> 
>>> +// Change Processor State is a system instruction -- for disassembly only.
>>> +// The singleton $opt operand contains the following information:
>>> +// opt{4-0} = mode from Inst{4-0}
>>> +// opt{5} = changemode from Inst{17}
>>> +// opt{8-6} = AIF from Inst{8-6}
>>> +// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
>>> +def CPS : AXI<(outs),(ins i32imm:$opt), Pseudo, NoItinerary, "cps${opt:cps}",
>>> +              [/* For disassembly only; pattern left blank */]>,
>>> +          Requires<[IsARM]> {
>>> +  let Inst{31-28} = 0b1111;
>>> +  let Inst{27-20} = 0b00010000;
>>> +  let Inst{16} = 0;
>>> +  let Inst{5} = 0;
>>> +}
>>> +
>>> def DBG : AI<(outs), (ins i32imm:$opt), Pseudo, NoItinerary, "dbg", "\t$opt",
>>>            [/* For disassembly only; pattern left blank */]>,
>>>         Requires<[IsARM, HasV7]> {
>>> @@ -2114,3 +2129,32 @@
>>> let Inst{23-20} = 0b0101;
>>> }
>>> 
>>> +//===----------------------------------------------------------------------===//
>>> +// Move between special register and ARM core register -- for disassembly only
>>> +//
>>> +
>>> +def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
>>> +              [/* For disassembly only; pattern left blank */]> {
>>> +  let Inst{23-20} = 0b0000;
>>> +  let Inst{7-4} = 0b0000;
>>> +}
>>> +
>>> +def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
>>> +              [/* For disassembly only; pattern left blank */]> {
>>> +  let Inst{23-20} = 0b0100;
>>> +  let Inst{7-4} = 0b0000;
>>> +}
>>> +
>>> +// FIXME: mask is ignored for the time being.
>>> +def MSR : ABI<0b0001,(outs),(ins GPR:$src), NoItinerary, "mrs", "\tcpsr, $src",
>>> +              [/* For disassembly only; pattern left blank */]> {
>>> +  let Inst{23-20} = 0b0010;
>>> +  let Inst{7-4} = 0b0000;
>>> +}
>>> +
>>> +// FIXME: mask is ignored for the time being.
>>> +def MSRsys : ABI<0b0001,(outs),(ins GPR:$src),NoItinerary,"mrs","\tspsr, $src",
>>> +              [/* For disassembly only; pattern left blank */]> {
>>> +  let Inst{23-20} = 0b0110;
>>> +  let Inst{7-4} = 0b0000;
>>> +}
>>> 
>>> 
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>> 
>