[llvm-commits] [llvm] r95957 - in /llvm/trunk/lib/Target/X86: X86.td X86InstrInfo.h

[Chris Lattner]

Author: lattner
Date: Thu Feb 11 19:55:31 2010
New Revision: 95957

URL: http://llvm.org/viewvc/llvm-project?rev=95957&view=rev
Log:
revert r95949, it turns out that adding new prefixes is not a 
great solution for the disassembler, we'll go with "plan b".

Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.h

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=95957&r1=95956&r2=95957&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Thu Feb 11 19:55:31 2010
@@ -168,11 +168,11 @@
                        6,
                        7,
                        8,
+                       12,
                        13,
-                       14,
-                       17,
+                       16,
+                       19,
                        20,
-                       21,
                        24];
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=95957&r1=95956&r2=95957&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Feb 11 19:55:31 2010
@@ -291,7 +291,7 @@
     // set, there is no prefix byte for obtaining a multibyte opcode.
     //
     Op0Shift    = 8,
-    Op0Mask     = 0x1F << Op0Shift,
+    Op0Mask     = 0xF << Op0Shift,
 
     // TB - TwoByte - Set if this instruction has a two byte opcode, which
     // starts with a 0x0F byte before the real opcode.
@@ -324,13 +324,13 @@
     // etc. We only cares about REX.W and REX.R bits and only the former is
     // statically determined.
     //
-    REXShift    = 13,
+    REXShift    = 12,
     REX_W       = 1 << REXShift,
 
     //===------------------------------------------------------------------===//
     // This three-bit field describes the size of an immediate operand.  Zero is
     // unused so that we can tell if we forgot to set a value.
-    ImmShift = 14,
+    ImmShift = 13,
     ImmMask  = 7 << ImmShift,
     Imm8     = 1 << ImmShift,
     Imm16    = 2 << ImmShift,
@@ -341,7 +341,7 @@
     // FP Instruction Classification...  Zero is non-fp instruction.
 
     // FPTypeMask - Mask for all of the FP types...
-    FPTypeShift = 17,
+    FPTypeShift = 16,
     FPTypeMask  = 7 << FPTypeShift,
 
     // NotFP - The default, set for instructions that do not use FP registers.
@@ -374,17 +374,17 @@
     SpecialFP  = 7 << FPTypeShift,
 
     // Lock prefix
-    LOCKShift = 20,
+    LOCKShift = 19,
     LOCK = 1 << LOCKShift,
 
     // Segment override prefixes. Currently we just need ability to address
     // stuff in gs and fs segments.
-    SegOvrShift = 21,
+    SegOvrShift = 20,
     SegOvrMask  = 3 << SegOvrShift,
     FS          = 1 << SegOvrShift,
     GS          = 2 << SegOvrShift,
 
-    // Bit 23 is unused.
+    // Bits 22 -> 23 are unused
     OpcodeShift   = 24,
     OpcodeMask    = 0xFF << OpcodeShift
   };