[llvm-commits] [llvm] r95867 - in /llvm/trunk/lib/Target/X86: X86CodeEmitter.cpp X86MCCodeEmitter.cpp

[Chris Lattner]

Author: lattner
Date: Thu Feb 11 02:45:56 2010
New Revision: 95867

URL: http://llvm.org/viewvc/llvm-project?rev=95867&view=rev
Log:
dont' call getX86RegNum on X86::RIP, it doesn't like that.  This
fixes the remaining x86-64 jit failures afaik.

Modified:
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=95867&r1=95866&r2=95867&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Thu Feb 11 02:45:56 2010
@@ -387,7 +387,9 @@
   // If no BaseReg, issue a RIP relative instruction only if the MCE can 
   // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
   // 2-7) and absolute references.
-  unsigned BaseRegNo = BaseReg != 0 ? getX86RegNum(BaseReg) : -1U;
+  unsigned BaseRegNo = -1U;
+  if (BaseReg != 0 && BaseReg != X86::RIP)
+    BaseRegNo = getX86RegNum(BaseReg);
 
   if (// The SIB byte must be used if there is an index register.
       IndexReg.getReg() == 0 && 

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=95867&r1=95866&r2=95867&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Thu Feb 11 02:45:56 2010
@@ -175,8 +175,10 @@
   const MCOperand &Scale    = MI.getOperand(Op+1);
   const MCOperand &IndexReg = MI.getOperand(Op+2);
   unsigned BaseReg = Base.getReg();
-  unsigned BaseRegNo = BaseReg != 0 ? GetX86RegNum(Base) : -1U;
-
+  unsigned BaseRegNo = -1U;
+  if (BaseReg != 0 && BaseReg != X86::RIP)
+    BaseRegNo = GetX86RegNum(Base);
+  
   // Determine whether a SIB byte is needed.
   // If no BaseReg, issue a RIP relative instruction only if the MCE can 
   // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table