[llvm-commits] [llvm] r94490 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/sext-i1.ll

[Evan Cheng]

On Jan 25, 2010, at 11:34 PM, Nate Begeman wrote:

> Hi Evan,
> 
> Doesn't this basically just undo the instcombine canonicalization in the DAG Combiner?  Why not match the sext(setcc()) pattern in the x86 codegen instead?

The instcombine canonicalization is meant to make other instcombine optimizations easier. On the other hand DAG combiner has more transformation rules for select_cc. At least on x86 and ARM, the later, i.e. (select_cc x, y, -1, 0, cc), generates better code.

Evan


> 
> Nate
> 
> On Jan 25, 2010, at 6:00 PM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Mon Jan 25 20:00:44 2010
>> New Revision: 94490
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=94490&view=rev
>> Log:
>> Implement cond ? -1 : 0 with sbb.
>> 
>> Added:
>>   llvm/trunk/test/CodeGen/X86/sext-i1.ll
>> Modified:
>>   llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>   llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=94490&r1=94489&r2=94490&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jan 25 20:00:44 2010
>> @@ -3220,6 +3220,14 @@
>>                       NegOne, DAG.getConstant(0, VT),
>>                       cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
>>    if (SCC.getNode()) return SCC;
>> +    if (!LegalOperations ||
>> +        TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
>> +      return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
>> +                         DAG.getSetCC(N->getDebugLoc(),
>> +                                      TLI.getSetCCResultType(VT),
>> +                                      N0.getOperand(0), N0.getOperand(1),
>> +                                 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
>> +                         NegOne, DAG.getConstant(0, VT));
>>  }
>> 
>> 
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=94490&r1=94489&r2=94490&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 25 20:00:44 2010
>> @@ -5965,6 +5965,29 @@
>>      Cond = NewCond;
>>  }
>> 
>> +  // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
>> +  SDValue Op1 = Op.getOperand(1);
>> +  SDValue Op2 = Op.getOperand(2);
>> +  if (Cond.getOpcode() == X86ISD::SETCC &&
>> +      cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
>> +    SDValue Cmp = Cond.getOperand(1);
>> +    if (Cmp.getOpcode() == X86ISD::CMP) {
>> +      ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
>> +      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
>> +      ConstantSDNode *RHSC =
>> +        dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
>> +      if (N1C && N1C->isAllOnesValue() &&
>> +          N2C && N2C->isNullValue() &&
>> +          RHSC && RHSC->isNullValue()) {
>> +        SDValue CmpOp0 = Cmp.getOperand(0);
>> +        Cmp = DAG.getNode(X86ISD::CMP, dl, Op.getValueType(),
>> +                          CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
>> +        return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
>> +                           DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
>> +      }
>> +    }
>> +  }
>> +
>>  // Look pass (and (setcc_carry (cmp ...)), 1).
>>  if (Cond.getOpcode() == ISD::AND &&
>>      Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
>> @@ -6017,10 +6040,10 @@
>>    Cond = EmitTest(Cond, X86::COND_NE, DAG);
>>  }
>> 
>> -  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
>>  // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
>>  // condition is true.
>> -  SDValue Ops[] = { Op.getOperand(2), Op.getOperand(1), CC, Cond };
>> +  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
>> +  SDValue Ops[] = { Op2, Op1, CC, Cond };
>>  return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
>> }
>> 
>> 
>> Added: llvm/trunk/test/CodeGen/X86/sext-i1.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-i1.ll?rev=94490&view=auto
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/sext-i1.ll (added)
>> +++ llvm/trunk/test/CodeGen/X86/sext-i1.ll Mon Jan 25 20:00:44 2010
>> @@ -0,0 +1,22 @@
>> +; RUN: llc < %s -march=x86 | FileCheck %s
>> +; rdar://7573216
>> +
>> +define i32 @t1(i32 %x) nounwind readnone ssp {
>> +entry:
>> +; CHECK: t1:
>> +; CHECK: cmpl $1
>> +; CHECK: sbbl
>> +  %0 = icmp eq i32 %x, 0
>> +  %iftmp.0.0 = select i1 %0, i32 -1, i32 0
>> +  ret i32 %iftmp.0.0
>> +}
>> +
>> +define i32 @t2(i32 %x) nounwind readnone ssp {
>> +entry:
>> +; CHECK: t2:
>> +; CHECK: cmpl $1
>> +; CHECK: sbbl
>> +  %0 = icmp eq i32 %x, 0
>> +  %iftmp.0.0 = sext i1 %0 to i32
>> +  ret i32 %iftmp.0.0
>> +}
>> 
>> 
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