[llvm-commits] [llvm] r94465 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

[Johnny Chen]

Author: johnny
Date: Mon Jan 25 16:54:29 2010
New Revision: 94465

URL: http://llvm.org/viewvc/llvm-project?rev=94465&view=rev
Log:
Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC.

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=94465&r1=94464&r2=94465&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Jan 25 16:54:29 2010
@@ -124,7 +124,7 @@
 //
 def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
                                            R7, R8, R9, R10, R11, R12,
-                                           LR, SP, PC]> {
+                                           SP, LR, PC]> {
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;