[llvm-commits] [llvm] r94455 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

[Johnny Chen]

Author: johnny
Date: Mon Jan 25 15:56:35 2010
New Revision: 94455

URL: http://llvm.org/viewvc/llvm-project?rev=94455&view=rev
Log:
Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ...

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=94455&r1=94454&r2=94455&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Jan 25 15:56:35 2010
@@ -123,7 +123,7 @@
 // r10 == Stack Limit
 //
 def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
-                                           R7, R8, R9, R10, R12, R11,
+                                           R7, R8, R9, R10, R11, R12,
                                            LR, SP, PC]> {
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;