[llvm-commits] [llvm-gcc-4.2] r93911 - in /llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon: vld2Qf32.c vld2Qp16.c vld2Qp8.c vld2Qs16.c vld2Qs32.c vld2Qs8.c vld2Qu16.c vld2Qu32.c vld2Qu8.c vst2Qf32.c vst2Qp16.c vst2Qp8.c vst2Qs16.c vst2Qs32.c vst2Qs8.c vst2Qu16.c vst2Qu32.c vst2Qu8.c
Bob Wilson
bob.wilson at apple.com
Tue Jan 19 13:17:11 PST 2010
Author: bwilson
Date: Tue Jan 19 15:17:10 2010
New Revision: 93911
URL: http://llvm.org/viewvc/llvm-project?rev=93911&view=rev
Log:
Fix the expected output for vld2Q and vst2Q tests. Both gcc and llvm-gcc
compile these intrinsics to a single vld2/vst2 instruction with 4 Neon register
operands. The expected output was looking for a pair of instructions each
taking 2 Neon registers.
Modified:
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_float32x4x2_t = vld2q_f32 (0);
}
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_poly16x8x2_t = vld2q_p16 (0);
}
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_poly8x16x2_t = vld2q_p8 (0);
}
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_int16x8x2_t = vld2q_s16 (0);
}
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_int32x4x2_t = vld2q_s32 (0);
}
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_int8x16x2_t = vld2q_s8 (0);
}
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_uint16x8x2_t = vld2q_u16 (0);
}
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_uint32x4x2_t = vld2q_u32 (0);
}
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c Tue Jan 19 15:17:10 2010
@@ -15,6 +15,6 @@
out_uint8x16x2_t = vld2q_u8 (0);
}
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VLD2 with 4 registers */
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
}
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
}
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
}
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
}
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
}
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
}
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
}
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
}
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c?rev=93911&r1=93910&r2=93911&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c Tue Jan 19 15:17:10 2010
@@ -16,6 +16,6 @@
vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
}
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* LLVM LOCAL Change to expect one VST2 with 4 registers */
+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
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