[llvm-commits] [llvm] r93773 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/xor.ll

[Evan Cheng]

Author: evancheng
Date: Mon Jan 18 15:38:44 2010
New Revision: 93773

URL: http://llvm.org/viewvc/llvm-project?rev=93773&view=rev
Log:
Canonicalize -1 - x to ~x.

Instcombine does this but apparently there are situations where this pattern will escape the optimizer and / or created by isel. Here is a case that's seen in JavaScriptCore:
  %t1 = sub i32 0, %a
  %t2 = add i32 %t1, -1
The dag combiner pattern: ((c1-A)+c2) -> (c1+c2)-A
will fold it to -1 - %a.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/xor.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=93773&r1=93772&r2=93773&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jan 18 15:38:44 2010
@@ -1176,6 +1176,9 @@
   if (N1C)
     return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
                        DAG.getConstant(-N1C->getAPIntValue(), VT));
+  // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
+  if (N0C && N0C->isAllOnesValue())
+    return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
   // fold (A+B)-A -> B
   if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
     return N0.getOperand(1);

Modified: llvm/trunk/test/CodeGen/X86/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=93773&r1=93772&r2=93773&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor.ll Mon Jan 18 15:38:44 2010
@@ -131,3 +131,14 @@
 ; X32:    andl	{{.*}}[[REG]]
 }
 
+define i32 @test8(i32 %a) nounwind {
+; rdar://7553032
+entry:
+  %t1 = sub i32 0, %a
+  %t2 = add i32 %t1, -1
+  ret i32 %t2
+; X64: test8:
+; X64:   notl %eax
+; X32: test8:
+; X32:   notl %eax
+}