[llvm-commits] [llvm] r93758 - in /llvm/trunk/lib/Target/ARM: ARMISelDAGToDAG.cpp ARMISelLowering.cpp ARMISelLowering.h ARMInstrInfo.td ARMInstrThumb2.td
Chris Lattner
clattner at apple.com
Mon Jan 18 12:35:29 PST 2010
Testcase?
On Jan 18, 2010, at 11:58 AM, Jim Grosbach wrote:
> Author: grosbach
> Date: Mon Jan 18 13:58:49 2010
> New Revision: 93758
>
> URL: http://llvm.org/viewvc/llvm-project?rev=93758&view=rev
> Log:
> Patch by David Conrad:
>
> "On ARMv6T2 this turns cttz into rbit, clz instead of the 4
> instruction
> sequence it is now."
>
>
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=93758&r1=93757&r2=93758&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Jan 18
> 13:58:49 2010
> @@ -1680,6 +1680,12 @@
> return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32,
> MVT::i32,
> N->getOperand(0), getAL(CurDAG),
> CurDAG->getRegister(0, MVT::i32));
> + case ARMISD::RBIT: {
> + EVT VT = N->getValueType(0);
> + SDValue Ops[] = { N->getOperand(0),
> + getAL(CurDAG), CurDAG->getRegister(0,
> MVT::i32) };
> + return CurDAG->getMachineNode(ARM::RBIT, dl, VT, Ops, 3);
> + }
> case ISD::UMUL_LOHI: {
> if (Subtarget->isThumb1Only())
> break;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=93758&r1=93757&r2=93758&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jan 18
> 13:58:49 2010
> @@ -340,7 +340,7 @@
>
> // ARM does not have ROTL.
> setOperationAction(ISD::ROTL, MVT::i32, Expand);
> - setOperationAction(ISD::CTTZ, MVT::i32, Expand);
> + setOperationAction(ISD::CTTZ, MVT::i32, Custom);
> setOperationAction(ISD::CTPOP, MVT::i32, Expand);
> if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
> setOperationAction(ISD::CTLZ, MVT::i32, Expand);
> @@ -482,6 +482,8 @@
> case ARMISD::CMOV: return "ARMISD::CMOV";
> case ARMISD::CNEG: return "ARMISD::CNEG";
>
> + case ARMISD::RBIT: return "ARMISD::RBIT";
> +
> case ARMISD::FTOSI: return "ARMISD::FTOSI";
> case ARMISD::FTOUI: return "ARMISD::FTOUI";
> case ARMISD::SITOF: return "ARMISD::SITOF";
> @@ -2231,6 +2233,18 @@
> return DAG.getMergeValues(Ops, 2, dl);
> }
>
> +static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
> + const ARMSubtarget *ST) {
> + EVT VT = N->getValueType(0);
> + DebugLoc dl = N->getDebugLoc();
> +
> + if (!ST->hasV6T2Ops())
> + return SDValue();
> +
> + SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
> + return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
> +}
> +
> static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
> const ARMSubtarget *ST) {
> EVT VT = N->getValueType(0);
> @@ -3016,6 +3030,7 @@
> case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
> case ISD::SRL_PARTS:
> case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
> + case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG,
> Subtarget);
> case ISD::VSETCC: return LowerVSETCC(Op, DAG);
> case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
> case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=93758&r1=93757&r2=93758&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Jan 18 13:58:49
> 2010
> @@ -53,6 +53,8 @@
> CMOV, // ARM conditional move instructions.
> CNEG, // ARM conditional negate instructions.
>
> + RBIT, // ARM bitreverse instruction
> +
> FTOSI, // FP to sint within a FP register.
> FTOUI, // FP to uint within a FP register.
> SITOF, // sint to FP within a FP register.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=93758&r1=93757&r2=93758&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jan 18 13:58:49 2010
> @@ -1455,6 +1455,13 @@
> let Inst{19-16} = 0b1111;
> }
>
> +def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
> IIC_iUNAr,
> + "rbit", "\t$dst, $src", []>, Requires<[IsARM,
> HasV6T2]> {
> + let Inst{7-4} = 0b0011;
> + let Inst{11-8} = 0b1111;
> + let Inst{19-16} = 0b1111;
> +}
> +
> def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
> IIC_iUNAr,
> "rev", "\t$dst, $src",
> [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM,
> HasV6]> {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=93758&r1=93757&r2=93758&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jan 18 13:58:49
> 2010
> @@ -1540,6 +1540,9 @@
> def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src),
> IIC_iUNAr,
> "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:
> $src))]>;
>
> +def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src),
> IIC_iUNAr,
> + "rbit", "\t$dst, $src", []>;
> +
> def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src),
> IIC_iUNAr,
> "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap
> GPR:$src))]>;
>
>
>
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